void mxr_reg_video_geo(struct mxr_device *mdev, int cur_mxr, int idx,
const struct mxr_geometry *geo)
{
u32 lt, rb;
unsigned long flags;
mxr_dbg(mdev, "%s\n", __func__);
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
lt = MXR_VIDEO_LT_LEFT_VAL(geo->dst.x_offset);
lt |= MXR_VIDEO_LT_TOP_VAL(geo->dst.y_offset);
rb = MXR_VIDEO_RB_RIGHT_VAL(geo->dst.x_offset + geo->dst.width - 1);
rb |= MXR_VIDEO_RB_BOTTOM_VAL(geo->dst.y_offset + geo->dst.height - 1);
if (cur_mxr == MXR_SUB_MIXER0) {
mxr_write(mdev, MXR_VIDEO_LT, lt);
mxr_write(mdev, MXR_VIDEO_RB, rb);
} else if (cur_mxr == MXR_SUB_MIXER1) {
mxr_write(mdev, MXR1_VIDEO_LT, lt);
mxr_write(mdev, MXR1_VIDEO_RB, rb);
}
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
mxr_dbg(mdev, "destination x = %d, y = %d, width = %d, height = %d\n",
geo->dst.x_offset, geo->dst.y_offset,
geo->dst.width, geo->dst.height);
}
void mxr_reg_graph_buffer(struct mxr_device *mdev, int idx, dma_addr_t addr)
{
u32 val = addr ? ~0 : 0;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
if (idx == 0) {
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
mxr_write(mdev, MXR_GRAPHIC_BASE(0), addr);
} else if (idx == 1) {
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
mxr_write(mdev, MXR_GRAPHIC_BASE(1), addr);
} else if (idx == 2) {
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_MX1_GRP0_ENABLE);
mxr_write(mdev, MXR1_GRAPHIC_BASE(0), addr);
} else if (idx == 3) {
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_MX1_GRP1_ENABLE);
mxr_write(mdev, MXR1_GRAPHIC_BASE(1), addr);
}
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_graph_format(struct mxr_device *mdev, int idx,
const struct mxr_format *fmt, const struct mxr_geometry *geo)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
/* setup format */
mxr_write_mask(mdev, MXR_GRAPHIC_CFG(idx),
MXR_GRP_CFG_FORMAT_VAL(fmt->cookie), MXR_GRP_CFG_FORMAT_MASK);
/* setup geometry */
mxr_write(mdev, MXR_GRAPHIC_SPAN(idx), geo->src.full_width);
val = MXR_GRP_WH_WIDTH(geo->src.width);
val |= MXR_GRP_WH_HEIGHT(geo->src.height);
val |= MXR_GRP_WH_H_SCALE(geo->x_ratio);
val |= MXR_GRP_WH_V_SCALE(geo->y_ratio);
mxr_write(mdev, MXR_GRAPHIC_WH(idx), val);
/* setup offsets in source image */
val = MXR_GRP_SXY_SX(geo->src.x_offset);
val |= MXR_GRP_SXY_SY(geo->src.y_offset);
mxr_write(mdev, MXR_GRAPHIC_SXY(idx), val);
/* setup offsets in display image */
val = MXR_GRP_DXY_DX(geo->dst.x_offset);
val |= MXR_GRP_DXY_DY(geo->dst.y_offset);
mxr_write(mdev, MXR_GRAPHIC_DXY(idx), val);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_set_color_range(struct mxr_device *mdev)
{
u32 val = 0;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
val = mdev->color_range;
mxr_write_mask(mdev, MXR_CFG, MXR_CFG_COLOR_RANGE(val),
MXR_CFG_COLOR_RANGE_MASK);
if (mdev->color_range == MIXER_RGB709_16_235 ||
mdev->color_range == MIXER_RGB601_16_235) {
val = MXR_VIDEO_LIMITER_PARA_Y_UPPER(235) |
MXR_VIDEO_LIMITER_PARA_Y_LOWER(16) |
MXR_VIDEO_LIMITER_PARA_C_UPPER(235) |
MXR_VIDEO_LIMITER_PARA_C_LOWER(16);
} else {
val = MXR_VIDEO_LIMITER_PARA_Y_UPPER(255) |
MXR_VIDEO_LIMITER_PARA_Y_LOWER(0) |
MXR_VIDEO_LIMITER_PARA_C_UPPER(255) |
MXR_VIDEO_LIMITER_PARA_C_LOWER(0);
}
mxr_write(mdev, MXR_VIDEO_LIMITER_PARA_CFG, val);
mxr_write_mask(mdev, MXR_VIDEO_CFG, 1,
MXR_VIDEO_CFG_LIMITER_EN);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
mxr_init_csc_coef(mdev);
}
irqreturn_t mxr_irq_handler(int irq, void *dev_data)
{
struct mxr_device *mdev = dev_data;
u32 val;
spin_lock(&mdev->reg_slock);
val = mxr_read(mdev, MXR_INT_STATUS);
/* wake up process waiting for VSYNC */
if (val & MXR_INT_STATUS_VSYNC) {
mdev->vsync_timestamp = ktime_get();
wake_up_interruptible_all(&mdev->vsync_wait);
}
/* clear interrupts.
vsync is updated after write MXR_CFG_LAYER_UPDATE bit */
if (val & MXR_INT_CLEAR_VSYNC)
mxr_write_mask(mdev, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
val = mxr_irq_underrun_handle(mdev, val);
mxr_write(mdev, MXR_INT_STATUS, val);
spin_unlock(&mdev->reg_slock);
return IRQ_HANDLED;
}
void mxr_reg_reset(struct mxr_device *mdev)
{
int i;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
/* set output in RGB888 mode */
mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_YUV444);
/* 16 beat burst in DMA */
mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,
MXR_STATUS_BURST_MASK);
for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i)
mxr_reg_sub_mxr_reset(mdev, i);
/* configuration of Video Processor Registers */
__mxr_reg_vp_reset(mdev);
mxr_reg_vp_default_filter(mdev);
/* enable all interrupts */
mxr_write_mask(mdev, MXR_INT_EN, ~0, MXR_INT_EN_ALL);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
irqreturn_t mxr_irq_handler(int irq, void *dev_data)
{
struct mxr_device *mdev = dev_data;
u32 i, val;
spin_lock(&mdev->reg_slock);
val = mxr_read(mdev, MXR_INT_STATUS);
if (val & MXR_INT_STATUS_VSYNC) {
set_bit(MXR_EVENT_VSYNC, &mdev->event_flags);
wake_up(&mdev->event_queue);
}
if (~val & MXR_INT_EN_VSYNC) {
val &= ~MXR_INT_EN_VSYNC;
val |= MXR_INT_CLEAR_VSYNC;
}
mxr_write(mdev, MXR_INT_STATUS, val);
spin_unlock(&mdev->reg_slock);
if (~val & MXR_INT_CLEAR_VSYNC)
return IRQ_HANDLED;
for (i = 0; i < MXR_MAX_LAYERS; ++i)
mxr_irq_layer_handle(mdev->layer[i]);
return IRQ_HANDLED;
}
irqreturn_t mxr_irq_handler(int irq, void *dev_data)
{
struct mxr_device *mdev = dev_data;
u32 i, val;
spin_lock(&mdev->reg_slock);
val = mxr_read(mdev, MXR_INT_STATUS);
/* wake up process waiting for VSYNC */
if (val & MXR_INT_STATUS_VSYNC) {
set_bit(MXR_EVENT_VSYNC, &mdev->event_flags);
/* toggle TOP field event if working in interlaced mode */
if (~mxr_read(mdev, MXR_CFG) & MXR_CFG_SCAN_PROGRASSIVE)
change_bit(MXR_EVENT_TOP, &mdev->event_flags);
wake_up(&mdev->event_queue);
/* vsync interrupt use different bit for read and clear */
val &= ~MXR_INT_STATUS_VSYNC;
val |= MXR_INT_CLEAR_VSYNC;
}
/* clear interrupts */
mxr_write(mdev, MXR_INT_STATUS, val);
spin_unlock(&mdev->reg_slock);
/* leave on non-vsync event */
if (~val & MXR_INT_CLEAR_VSYNC)
return IRQ_HANDLED;
/* skip layer update on bottom field */
if (!test_bit(MXR_EVENT_TOP, &mdev->event_flags))
return IRQ_HANDLED;
for (i = 0; i < MXR_MAX_LAYERS; ++i)
mxr_irq_layer_handle(mdev->layer[i]);
return IRQ_HANDLED;
}
void mxr_reg_local_path_set(struct mxr_device *mdev)
{
struct sub_mxr_device *mxr0 = &mdev->sub_mxr[MXR_SUB_MIXER0];
struct sub_mxr_device *mxr1 = &mdev->sub_mxr[MXR_SUB_MIXER1];
u32 val = 0;
if (mxr0->local && !mxr1->local) { /* 1-path : sub-mixer0 */
val = MXR_TVOUT_CFG_ONE_PATH;
val |= MXR_TVOUT_CFG_PATH_MIXER0;
} else if (!mxr0->local && mxr1->local) { /* 1-path : sub-mixer1 */
val = MXR_TVOUT_CFG_ONE_PATH;
val |= MXR_TVOUT_CFG_PATH_MIXER1;
} else if (mxr0->local && mxr1->local) { /* 2-path */
val = MXR_TVOUT_CFG_TWO_PATH;
val |= MXR_TVOUT_CFG_STEREO_SCOPIC;
}
mxr_write(mdev, MXR_TVOUT_CFG, val);
/* set local path gscaler to mixer */
val = readl(SYSREG_DISP1BLK_CFG);
val &= ~DISP1BLK_CFG_MIXER_MASK;
if (mdev->flags & MEDIA_LNK_FL_ENABLED) {
if (mxr0->local) {
val |= DISP1BLK_CFG_MIXER0_VALID;
val |= DISP1BLK_CFG_MIXER0_SRC_GSC(mxr0->gsc_num);
}
if (mxr1->local) {
val |= DISP1BLK_CFG_MIXER1_VALID;
val |= DISP1BLK_CFG_MIXER1_SRC_GSC(mxr1->gsc_num);
}
}
mxr_dbg(mdev, "%s: SYSREG value = 0x%x\n", __func__, val);
writel(val, SYSREG_DISP1BLK_CFG);
}
void mxr_reg_graph_chromakey_value(struct mxr_device *mdev, int idx,u32 en)
{
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_write(mdev,MXR_GRAPHIC_BLANK(idx),en);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_graph_buffer(struct mxr_device *mdev, int idx, dma_addr_t addr)
{
u32 val = addr ? ~0 : 0;
if (idx == 0) {
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
mxr_write(mdev, MXR_GRAPHIC_BASE(0), addr);
} else if (idx == 1) {
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
mxr_write(mdev, MXR_GRAPHIC_BASE(1), addr);
} else if (idx == 2) {
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_MX1_GRP0_ENABLE);
mxr_write(mdev, MXR1_GRAPHIC_BASE(0), addr);
} else if (idx == 3) {
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_MX1_GRP1_ENABLE);
mxr_write(mdev, MXR1_GRAPHIC_BASE(1), addr);
}
}
/*set mixer resolution */
void mxr_reg_set_resolution(struct mxr_device *mdev)
{
u32 mxr_wh;
struct v4l2_mbus_framefmt mbus_fmt;
mxr_get_mbus_fmt(mdev, &mbus_fmt);
mxr_wh = MXR_RESOLUTION_WIDTH(mbus_fmt.width);
mxr_wh |= MXR_RESOLUTION_HEIGHT(mbus_fmt.height);
mxr_write(mdev, MXR_RESOLUTION, mxr_wh);
}
void mxr_reg_vp_priority(struct mxr_device *mdev, int idx,u32 en)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
val=mxr_read(mdev,MXR_LAYER_CFG);
BF_SET(val,en,0,4);
mxr_write(mdev, MXR_LAYER_CFG, val);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_vp_layer_blend_alpha(struct mxr_device *mdev , int idx, u32 en)
{
unsigned long flags;
int val;
spin_lock_irqsave(&mdev->reg_slock, flags);
val = mxr_read(mdev,MXR_VIDEO_CFG);
BF_SET(val,en,0,8);
mxr_write(mdev,MXR_VIDEO_CFG,val);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_colorkey_val(struct mxr_device *mdev, int sub_mxr, int num, u32 v)
{
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP0)
mxr_write(mdev, MXR_GRAPHIC_BLANK(0), v);
else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP1)
mxr_write(mdev, MXR_GRAPHIC_BLANK(1), v);
#if defined(CONFIG_ARCH_EXYNOS5)
else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP0)
mxr_write(mdev, MXR1_GRAPHIC_BLANK(0), v);
else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP1)
mxr_write(mdev, MXR1_GRAPHIC_BLANK(1), v);
#endif
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_reset(struct mxr_device *mdev)
{
unsigned long flags;
u32 val; /* value stored to register */
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
/* set output in RGB888 mode */
mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888);
/* 16 beat burst in DMA */
mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,
MXR_STATUS_BURST_MASK);
/* setting default layer priority: layer1 > video > layer0
* because typical usage scenario would be
* layer0 - framebuffer
* video - video overlay
* layer1 - OSD
*/
val = MXR_LAYER_CFG_GRP0_VAL(1);
val |= MXR_LAYER_CFG_VP_VAL(2);
val |= MXR_LAYER_CFG_GRP1_VAL(3);
mxr_write(mdev, MXR_LAYER_CFG, val);
/* use dark teal background color */
mxr_write(mdev, MXR_BG_COLOR0, 0x008080);
mxr_write(mdev, MXR_BG_COLOR1, 0x008080);
mxr_write(mdev, MXR_BG_COLOR2, 0x008080);
/* setting graphical layers */
val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
val |= MXR_GRP_CFG_LAYER_BLEND_EN;
val &= ~MXR_GRP_CFG_BLEND_PRE_MUL; /* normal mode */
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
/* the same configuration for both layers */
mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);
/* configuration of Video Processor Registers */
__mxr_reg_vp_reset(mdev);
mxr_reg_vp_default_filter(mdev);
/* enable all interrupts */
mxr_write_mask(mdev, MXR_INT_EN, ~0, MXR_INT_EN_ALL);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_graph_priority(struct mxr_device *mdev, int idx,u32 en)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
val = mxr_read(mdev,MXR_LAYER_CFG);
if(idx==0)
BF_SET(val,en,4,4); /*for grapics later 0*/
else
BF_SET(val,en,8,4); /*for grapics later 1*/
mxr_write(mdev, MXR_LAYER_CFG, val);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_graph_chromakey_enable(struct mxr_device *mdev, int idx,u32 en)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
val=(u32)mxr_read(mdev,MXR_GRAPHIC_CFG(idx));
if (en)
val &= ~MXR_GRP_CFG_COLOR_KEY_DISABLE;
else
val |= MXR_GRP_CFG_COLOR_KEY_DISABLE;
mxr_write(mdev,MXR_GRAPHIC_CFG(idx),val);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_set_layer_prio(struct mxr_device *mdev)
{
u8 p_g0, p_g1, p_v;
u32 val;
p_v = mdev->sub_mxr[MXR_SUB_MIXER0].layer[MXR_LAYER_VIDEO]->prio;
p_g0 = mdev->sub_mxr[MXR_SUB_MIXER0].layer[MXR_LAYER_GRP0]->prio;
p_g1 = mdev->sub_mxr[MXR_SUB_MIXER0].layer[MXR_LAYER_GRP1]->prio;
mxr_dbg(mdev, "video layer priority = %d\n", p_v);
mxr_dbg(mdev, "graphic0 layer priority = %d\n", p_g0);
mxr_dbg(mdev, "graphic1 layer priority = %d\n", p_g1);
val = MXR_LAYER_CFG_GRP1_VAL(p_g1);
val |= MXR_LAYER_CFG_GRP0_VAL(p_g0);
val |= MXR_LAYER_CFG_VP_VAL(p_v);
mxr_write(mdev, MXR_LAYER_CFG, val);
}
void mxr_reg_reset(struct mxr_device *mdev)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888);
mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,
MXR_STATUS_BURST_MASK);
val = MXR_LAYER_CFG_GRP0_VAL(1);
val |= MXR_LAYER_CFG_VP_VAL(2);
val |= MXR_LAYER_CFG_GRP1_VAL(3);
mxr_write(mdev, MXR_LAYER_CFG, val);
mxr_write(mdev, MXR_BG_COLOR0, 0x808080);
mxr_write(mdev, MXR_BG_COLOR1, 0x808080);
mxr_write(mdev, MXR_BG_COLOR2, 0x808080);
val = MXR_GRP_CFG_COLOR_KEY_DISABLE;
val |= MXR_GRP_CFG_BLEND_PRE_MUL;
val |= MXR_GRP_CFG_ALPHA_VAL(0xff);
mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);
__mxr_reg_vp_reset(mdev);
mxr_reg_vp_default_filter(mdev);
mxr_write_mask(mdev, MXR_INT_EN, ~0, MXR_INT_EN_ALL);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_graph_layer_stream(struct mxr_device *mdev, int idx, int en)
{
u32 val = 0;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
if (mdev->frame_packing) {
val = MXR_TVOUT_CFG_TWO_PATH;
val |= MXR_TVOUT_CFG_STEREO_SCOPIC;
} else {
val = MXR_TVOUT_CFG_ONE_PATH;
val |= MXR_TVOUT_CFG_PATH_MIXER0;
}
mxr_write(mdev, MXR_TVOUT_CFG, val);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
irqreturn_t mxr_irq_handler(int irq, void *dev_data)
{
struct mxr_device *mdev = dev_data;
u32 i, val;
spin_lock(&mdev->reg_slock);
val = mxr_read(mdev, MXR_INT_STATUS);
/* wake up process waiting for VSYNC */
if (val & MXR_INT_STATUS_VSYNC) {
set_bit(MXR_EVENT_VSYNC, &mdev->event_flags);
wake_up(&mdev->event_queue);
}
/* clear interrupts */
if (~val & MXR_INT_EN_VSYNC) {
/* vsync interrupt use different bit for read and clear */
val &= ~MXR_INT_EN_VSYNC;
val |= MXR_INT_CLEAR_VSYNC;
}
val = mxr_irq_underrun_handle(mdev, val);
mxr_write(mdev, MXR_INT_STATUS, val);
spin_unlock(&mdev->reg_slock);
/* leave on non-vsync event */
if (~val & MXR_INT_CLEAR_VSYNC)
return IRQ_HANDLED;
for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i) {
#if defined(CONFIG_ARCH_EXYNOS4)
mxr_irq_layer_handle(mdev->sub_mxr[i].layer[MXR_LAYER_VIDEO]);
#endif
mxr_irq_layer_handle(mdev->sub_mxr[i].layer[MXR_LAYER_GRP0]);
mxr_irq_layer_handle(mdev->sub_mxr[i].layer[MXR_LAYER_GRP1]);
}
return IRQ_HANDLED;
}
static void mxr_reg_sub_mxr_reset(struct mxr_device *mdev, int mxr_num)
{
u32 val; /* value stored to register */
if (mxr_num == MXR_SUB_MIXER0) {
/* setting default layer priority: layer1 > video > layer0
* because typical usage scenario would be
* layer0 - framebuffer
* video - video overlay
* layer1 - OSD
*/
val = MXR_LAYER_CFG_GRP0_VAL(1);
val |= MXR_LAYER_CFG_VP_VAL(2);
val |= MXR_LAYER_CFG_GRP1_VAL(3);
mxr_write(mdev, MXR_LAYER_CFG, val);
/* use dark gray background color */
mxr_write(mdev, MXR_BG_COLOR0, 0x008080);
mxr_write(mdev, MXR_BG_COLOR1, 0x008080);
mxr_write(mdev, MXR_BG_COLOR2, 0x008080);
/* setting graphical layers */
val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
val |= MXR_GRP_CFG_BLEND_PRE_MUL; /* premul mode */
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
/* the same configuration for both layers */
mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);
} else if (mxr_num == MXR_SUB_MIXER1) {
val = MXR_LAYER_CFG_GRP0_VAL(1);
val |= MXR_LAYER_CFG_VP_VAL(2);
val |= MXR_LAYER_CFG_GRP1_VAL(3);
mxr_write(mdev, MXR1_LAYER_CFG, val);
/* use dark gray background color */
mxr_write(mdev, MXR1_BG_COLOR0, 0x008080);
mxr_write(mdev, MXR1_BG_COLOR1, 0x008080);
mxr_write(mdev, MXR1_BG_COLOR2, 0x008080);
/* setting graphical layers */
val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
val |= MXR_GRP_CFG_BLEND_PRE_MUL; /* premul mode */
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
/* the same configuration for both layers */
mxr_write(mdev, MXR1_GRAPHIC_CFG(0), val);
mxr_write(mdev, MXR1_GRAPHIC_CFG(1), val);
}
}
void mxr_reg_graph_format(struct mxr_device *mdev, int idx,
const struct mxr_format *fmt, const struct mxr_geometry *geo)
{
u32 wh, sxy, dxy;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
/* Mostly, src width, height and dst width, height are same.
* However, in case of doing src and dst cropping, those are different.
* So you have to write dst width and height to MXR_GRAPHIC_WH register.
*/
wh = MXR_GRP_WH_WIDTH(geo->dst.width);
wh |= MXR_GRP_WH_HEIGHT(geo->dst.height);
wh |= MXR_GRP_WH_H_SCALE(geo->x_ratio);
wh |= MXR_GRP_WH_V_SCALE(geo->y_ratio);
/* setup offsets in source image */
sxy = MXR_GRP_SXY_SX(geo->src.x_offset);
sxy |= MXR_GRP_SXY_SY(geo->src.y_offset);
/* setup offsets in display image */
dxy = MXR_GRP_DXY_DX(geo->dst.x_offset);
dxy |= MXR_GRP_DXY_DY(geo->dst.y_offset);
if (idx == 0) {
mxr_write_mask(mdev, MXR_GRAPHIC_CFG(0),
MXR_GRP_CFG_FORMAT_VAL(fmt->cookie),
MXR_GRP_CFG_FORMAT_MASK);
mxr_write(mdev, MXR_GRAPHIC_SPAN(0), geo->src.full_width);
mxr_write(mdev, MXR_GRAPHIC_WH(0), wh);
mxr_write(mdev, MXR_GRAPHIC_SXY(0), sxy);
mxr_write(mdev, MXR_GRAPHIC_DXY(0), dxy);
} else if (idx == 1) {
mxr_write_mask(mdev, MXR_GRAPHIC_CFG(1),
MXR_GRP_CFG_FORMAT_VAL(fmt->cookie),
MXR_GRP_CFG_FORMAT_MASK);
mxr_write(mdev, MXR_GRAPHIC_SPAN(1), geo->src.full_width);
mxr_write(mdev, MXR_GRAPHIC_WH(1), wh);
mxr_write(mdev, MXR_GRAPHIC_SXY(1), sxy);
mxr_write(mdev, MXR_GRAPHIC_DXY(1), dxy);
} else if (idx == 2) {
mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(0),
MXR_GRP_CFG_FORMAT_VAL(fmt->cookie),
MXR_GRP_CFG_FORMAT_MASK);
mxr_write(mdev, MXR1_GRAPHIC_SPAN(0), geo->src.full_width);
mxr_write(mdev, MXR1_GRAPHIC_WH(0), wh);
mxr_write(mdev, MXR1_GRAPHIC_SXY(0), sxy);
mxr_write(mdev, MXR1_GRAPHIC_DXY(0), dxy);
} else if (idx == 3) {
mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(1),
MXR_GRP_CFG_FORMAT_VAL(fmt->cookie),
MXR_GRP_CFG_FORMAT_MASK);
mxr_write(mdev, MXR1_GRAPHIC_SPAN(1), geo->src.full_width);
mxr_write(mdev, MXR1_GRAPHIC_WH(1), wh);
mxr_write(mdev, MXR1_GRAPHIC_SXY(1), sxy);
mxr_write(mdev, MXR1_GRAPHIC_DXY(1), dxy);
}
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
static void mxr_reg_sub_mxr_reset(struct mxr_device *mdev, int mxr_num)
{
u32 val; /* value stored to register */
if (mxr_num == MXR_SUB_MIXER0) {
/* use dark gray background color */
mxr_write(mdev, MXR_BG_COLOR0, 0x008080);
mxr_write(mdev, MXR_BG_COLOR1, 0x008080);
mxr_write(mdev, MXR_BG_COLOR2, 0x008080);
/* setting graphical layers */
val = MXR_GRP_CFG_BLANK_KEY_EN; /* no blank key */
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
/* the same configuration for both layers */
mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);
} else if (mxr_num == MXR_SUB_MIXER1) {
val = MXR_LAYER_CFG_GRP1_VAL(3);
val |= MXR_LAYER_CFG_GRP0_VAL(2);
val |= MXR_LAYER_CFG_VP_VAL(1);
mxr_write(mdev, MXR1_LAYER_CFG, val);
/* use dark gray background color */
mxr_write(mdev, MXR1_BG_COLOR0, 0x008080);
mxr_write(mdev, MXR1_BG_COLOR1, 0x008080);
mxr_write(mdev, MXR1_BG_COLOR2, 0x008080);
/* setting graphical layers */
val = MXR_GRP_CFG_BLANK_KEY_EN; /* no blank key */
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
/* the same configuration for both layers */
mxr_write(mdev, MXR1_GRAPHIC_CFG(0), val);
mxr_write(mdev, MXR1_GRAPHIC_CFG(1), val);
}
}
void mxr_init_csc_coef(struct mxr_device *mdev)
{
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
switch (mdev->color_range) {
case MIXER_RGB601_0_255:
mxr_write(mdev, MXR_CM_COEFF_Y,
(1 << 30) | (132 << 20) | (258 << 10) | (50 << 0));
mxr_write(mdev, MXR_CM_COEFF_CB,
(948 << 20) | (875 << 10) | (225 << 0));
mxr_write(mdev, MXR_CM_COEFF_CR,
(225 << 20) | (836 << 10) | (988 << 0));
break;
case MIXER_RGB601_16_235:
mxr_write(mdev, MXR_CM_COEFF_Y,
(0 << 30) | (153 << 20) | (300 << 10) | (58 << 0));
mxr_write(mdev, MXR_CM_COEFF_CB,
(936 << 20) | (851 << 10) | (262 << 0));
mxr_write(mdev, MXR_CM_COEFF_CR,
(262 << 20) | (805 << 10) | (982 << 0));
break;
case MIXER_RGB709_0_255:
mxr_write(mdev, MXR_CM_COEFF_Y,
(1 << 30) | (94 << 20) | (314 << 10) | (32 << 0));
mxr_write(mdev, MXR_CM_COEFF_CB,
(972 << 20) | (851 << 10) | (225 << 0));
mxr_write(mdev, MXR_CM_COEFF_CR,
(225 << 20) | (820 << 10) | (1004 << 0));
break;
case MIXER_RGB709_16_235:
mxr_write(mdev, MXR_CM_COEFF_Y,
(0 << 30) | (109 << 20) | (366 << 10) | (36 << 0));
mxr_write(mdev, MXR_CM_COEFF_CB,
(964 << 20) | (822 << 10) | (216 << 0));
mxr_write(mdev, MXR_CM_COEFF_CR,
(262 << 20) | (787 << 10) | (1000 << 0));
break;
default:
mxr_err(mdev, "invalid csc_type parameter");
break;
}
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}