static int n1_panel_disable(void)
{
//Display off
{
n1_spi_write( 0, 0x28 );
}
msleep(25);//25ms
//Sleep In
{
n1_spi_write( 0, 0x10 );
}
msleep(150);//150ms
// gpio_set_value(GPIO_LCD_LDO_LED_EN, 0);
gpio_set_value(n1_lvds_reset, 0);
usleep_range(5000, 6000);//5ms
regulator_disable(reg_lcd_3v0);
regulator_disable(reg_lcd_1v8);
#if defined (CONFIG_MACH_BOSE_ATT)
muxtex_temp = 0 ;
#endif
return 0;
}
int n1_panel_disable(void)
{
//Display off
{
n1_spi_write( 0, 0x28 );
}
msleep(25);//25ms
//Sleep In
{
n1_spi_write( 0, 0x10 );
}
msleep(150);//150ms
gpio_set_value(GPIO_LCD_LDO_LED_EN, 0);
gpio_set_value(n1_lvds_reset, 0);
usleep_range(5000, 6000);//5ms
regulator_disable(reg_lcd_3v0);
regulator_disable(reg_lcd_1v8);
return 0;
}
static int n1_panel_enable(void)
{
regulator_enable(reg_lcd_1v8);
regulator_enable(reg_lcd_3v0);
usleep_range(2000, 3000);//2ms
/* take panel out of reset */
gpio_set_value(n1_lvds_reset, 1);
msleep(50);//50ms
//Set address mode
{
n1_spi_write( 0, 0x36 );
if(system_rev==0 || system_rev==-1)
{
n1_spi_write( 1, 0x44 );
}
else
{
n1_spi_write( 1, 0xD4 );
}
}
msleep(25);//25ms
//Sleep Out Command
{
n1_spi_write( 0, 0x11 );
}
msleep(40);//40ms
//Display On Command
{
n1_spi_write( 0, 0x29 );
}
// gpio_set_value(GPIO_LCD_LDO_LED_EN, 1);
return 0;
}
int n1_panel_enable(void)
{
regulator_enable(reg_lcd_1v8);
regulator_enable(reg_lcd_3v0);
mdelay(10);
/* take panel out of reset */
gpio_set_value(n1_lvds_reset, 1);
//gpio_set_value(GPIO_LCD_LDO_LED_EN, 1);
#ifdef CONFIG_MACH_N1_CHN
msleep(10);//10ms
//Pushing DC data out 10 msec after from LCD reset.
tegra_fb_dc_data_out(registered_fb[0]);
msleep(40);//40ms
#else
msleep(50);//50ms
#endif
msleep(50);//50ms
msleep(10);//50ms
//Set address mode
{
n1_spi_write( 0, 0x36 );
#if USE_CHECK_HW_REVERSION
if(system_rev==0 || system_rev==-1)
{
n1_spi_write( 1, 0x44 );
}
else
{
n1_spi_write( 1, 0xD4 );
}
#else
n1_spi_write( 1, 0xD4 );
#endif
}
msleep(25);//25ms
//Sleep Out Command
{
n1_spi_write( 0, 0x11 );
}
msleep(150);//150ms
//Display On Command
{
n1_spi_write( 0, 0x29 );
}
gpio_set_value(GPIO_LCD_LDO_LED_EN, 1);
return 0;
}
static int n1_panel_enable(void)
{
printk(KERN_INFO "%s: start\n", __func__);
regulator_enable(reg_lcd_1v8);
mdelay(1);
printk(KERN_INFO "%s: regulator_enable(reg_lcd_1v8);\n", __func__);
regulator_enable(reg_lcd_3v0);
mdelay(1);
printk(KERN_INFO "%s: regulator_enable(reg_lcd_3v0);\n", __func__);
/* take panel out of reset */
gpio_set_value(n1_lvds_reset, 1);
mdelay(50);
printk(KERN_INFO "%s: gpio_set_value(n1_lvds_reset, 1);\n", __func__);
//SEQ_USER_SETTING
n1_spi_write( 0, 0xF0 );
n1_spi_write( 1, 0x5A );
n1_spi_write( 1, 0x5A );
//SEQ_DISPCTL
n1_spi_write( 0, 0xF2 );
n1_spi_write( 1, 0x02 );
n1_spi_write( 1, 0x06 );
n1_spi_write( 1, 0x0A );
n1_spi_write( 1, 0x10 );
n1_spi_write( 1, 0x10 );
//SEQ_GTCON
n1_spi_write( 0, 0xF7 );
n1_spi_write( 1, 0x09 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
//SEQ_PANEL_CONDITION
n1_spi_write( 0, 0xF8 );
n1_spi_write( 1, 0x05 );
n1_spi_write( 1, 0x5E );
n1_spi_write( 1, 0x96 );
n1_spi_write( 1, 0x6B );
n1_spi_write( 1, 0x7D );
n1_spi_write( 1, 0x0D );
n1_spi_write( 1, 0x3F );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x32 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x07 );
n1_spi_write( 1, 0x07 );
n1_spi_write( 1, 0x20 );
n1_spi_write( 1, 0x20 );
n1_spi_write( 1, 0x20 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
//SEQ_SLPOUT
n1_spi_write( 0, 0x11 );
n1_spi_write( 1, 0x09 );
mdelay(120);//Wait 120ms
//SEQ_ELVSS_ON_SM2
n1_spi_write( 0, 0xB1 );
n1_spi_write( 1, 0x0F );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x16 );
n1_spi_write( 0, 0xB2 );
n1_spi_write( 1, 0x15 );
n1_spi_write( 1, 0x15 );
n1_spi_write( 1, 0x15 );
//SEQ_PWR_CTRL_SM2
n1_spi_write( 0, 0xF4 );
n1_spi_write( 1, 0x0A );
n1_spi_write( 1, 0x87 );
n1_spi_write( 1, 0x25 );
n1_spi_write( 1, 0x6A );
n1_spi_write( 1, 0x44 );
n1_spi_write( 1, 0x02 );
//SEQ_GAMMA_SET1_SM2
n1_spi_write( 0, 0xF9 );
n1_spi_write( 1, 0x2E );
n1_spi_write( 1, 0xB1 );
n1_spi_write( 1, 0xB3 );
n1_spi_write( 1, 0xAD );
n1_spi_write( 1, 0xBF );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x8E );
n1_spi_write( 1, 0x36 );
n1_spi_write( 1, 0xA3 );
n1_spi_write( 1, 0xA9 );
n1_spi_write( 1, 0xA6 );
n1_spi_write( 1, 0xBB );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0xA3 );
n1_spi_write( 1, 0x2E );
n1_spi_write( 1, 0xAC );
n1_spi_write( 1, 0xAD );
n1_spi_write( 1, 0xA8 );
n1_spi_write( 1, 0xBC );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0xB4 );
//SEQ_GAMMA_CTRL
n1_spi_write( 0, 0xFB );
n1_spi_write( 1, 0x02 );
n1_spi_write( 1, 0x5A );
//SEQ_DISPON
n1_spi_write( 0, 0x29 );
return 0;
}
static int n1_panel_enable(void)
{
regulator_enable(reg_lcd_1v8);
msleep(1);
regulator_enable(reg_lcd_3v0);
msleep(1);
msleep(25);
/* take panel out of reset */
gpio_set_value(n1_lvds_reset, 1);
//Wait 10ms
msleep( 10 );
printk("n1_panel_enable..%d\n",__LINE__);
//Panel Condition Set
{
n1_spi_write( 0, 0xF8 );
n1_spi_write( 1, 0x01 );
n1_spi_write( 1, 0x27 );
n1_spi_write( 1, 0x27 );
n1_spi_write( 1, 0x07 );
n1_spi_write( 1, 0x07 );
n1_spi_write( 1, 0x54 );
n1_spi_write( 1, 0x9F );
n1_spi_write( 1, 0x63 );
n1_spi_write( 1, 0x86 );
// n1_spi_write( 1, 0x8F );
n1_spi_write( 1, 0x1A );
n1_spi_write( 1, 0x33 );
n1_spi_write( 1, 0x0D );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
}
//Display Condition Set
{
//1) Display Control Set
n1_spi_write( 0, 0xF2 );
n1_spi_write( 1, 0x02 );
n1_spi_write( 1, 0x03 );
n1_spi_write( 1, 0x1C );
n1_spi_write( 1, 0x10 );
n1_spi_write( 1, 0x10 );
n1_spi_write( 0, 0xF7 );
n1_spi_write( 1, 0x00 );
//n1_spi_write( 1, 0x03 ); //In order to have vertical flip
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
}
//Gamma Condition Set
{
{
//1) Gamma Setting
n1_spi_write( 0, 0xFA );
n1_spi_write( 1, 0x02 );
n1_spi_write( 1, 0x18 );
n1_spi_write( 1, 0x08 );
n1_spi_write( 1, 0x24 );
n1_spi_write( 1, 0x70 );
n1_spi_write( 1, 0x6E );
n1_spi_write( 1, 0x4E );
n1_spi_write( 1, 0xBC );
n1_spi_write( 1, 0xC0 );
n1_spi_write( 1, 0xAF );
n1_spi_write( 1, 0xB3 );
n1_spi_write( 1, 0xB8 );
n1_spi_write( 1, 0xA5 );
n1_spi_write( 1, 0xC5 );
n1_spi_write( 1, 0xC7 );
n1_spi_write( 1, 0xBB );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0xB9 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0xB8 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0xFC );
}
{
//2) Gamma Set Update
n1_spi_write( 0, 0xFA );
// n1_spi_write( 1, 0x01 );
n1_spi_write( 1, 0x03 );
}
}
//ETC Condition Set
{
{
//1)
n1_spi_write( 0, 0xF6 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x8E );
n1_spi_write( 1, 0x07 );
}
{
//2)
n1_spi_write( 0, 0xB3 );
n1_spi_write( 1, 0x6C );
}
{
//3)
n1_spi_write( 0, 0xB5 );
n1_spi_write( 1, 0x2C );
n1_spi_write( 1, 0x12 );
n1_spi_write( 1, 0x0C );
n1_spi_write( 1, 0x0A );
n1_spi_write( 1, 0x10 );
n1_spi_write( 1, 0x0E );
n1_spi_write( 1, 0x17 );
n1_spi_write( 1, 0x13 );
n1_spi_write( 1, 0x1F );
n1_spi_write( 1, 0x1A );
n1_spi_write( 1, 0x2A );
n1_spi_write( 1, 0x24 );
n1_spi_write( 1, 0x1F );
n1_spi_write( 1, 0x1B );
n1_spi_write( 1, 0x1A );
n1_spi_write( 1, 0x17 );
n1_spi_write( 1, 0x2B );
n1_spi_write( 1, 0x26 );
n1_spi_write( 1, 0x22 );
n1_spi_write( 1, 0x20 );
n1_spi_write( 1, 0x3A );
n1_spi_write( 1, 0x34 );
n1_spi_write( 1, 0x30 );
n1_spi_write( 1, 0x2C );
n1_spi_write( 1, 0x29 );
n1_spi_write( 1, 0x26 );
n1_spi_write( 1, 0x25 );
n1_spi_write( 1, 0x23 );
n1_spi_write( 1, 0x21 );
n1_spi_write( 1, 0x20 );
n1_spi_write( 1, 0x1E );
n1_spi_write( 1, 0x1E );
}
{
//4)
n1_spi_write( 0, 0xB6 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x11 );
n1_spi_write( 1, 0x22 );
n1_spi_write( 1, 0x33 );
n1_spi_write( 1, 0x44 );
n1_spi_write( 1, 0x44 );
n1_spi_write( 1, 0x44 );
n1_spi_write( 1, 0x55 );
n1_spi_write( 1, 0x55 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
}
{
//5)
n1_spi_write( 0, 0xB7 );
n1_spi_write( 1, 0x2C );
n1_spi_write( 1, 0x12 );
n1_spi_write( 1, 0x0C );
n1_spi_write( 1, 0x0A );
n1_spi_write( 1, 0x10 );
n1_spi_write( 1, 0x0E );
n1_spi_write( 1, 0x17 );
n1_spi_write( 1, 0x13 );
n1_spi_write( 1, 0x1F );
n1_spi_write( 1, 0x1A );
n1_spi_write( 1, 0x2A );
n1_spi_write( 1, 0x24 );
n1_spi_write( 1, 0x1F );
n1_spi_write( 1, 0x1B );
n1_spi_write( 1, 0x1A );
n1_spi_write( 1, 0x17 );
n1_spi_write( 1, 0x2B );
n1_spi_write( 1, 0x26 );
n1_spi_write( 1, 0x22 );
n1_spi_write( 1, 0x20 );
n1_spi_write( 1, 0x3A );
n1_spi_write( 1, 0x34 );
n1_spi_write( 1, 0x30 );
n1_spi_write( 1, 0x2C );
n1_spi_write( 1, 0x29 );
n1_spi_write( 1, 0x26 );
n1_spi_write( 1, 0x25 );
n1_spi_write( 1, 0x23 );
n1_spi_write( 1, 0x21 );
n1_spi_write( 1, 0x20 );
n1_spi_write( 1, 0x1E );
n1_spi_write( 1, 0x1E );
}
{
//6)
n1_spi_write( 0, 0xB8 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x11 );
n1_spi_write( 1, 0x22 );
n1_spi_write( 1, 0x33 );
n1_spi_write( 1, 0x44 );
n1_spi_write( 1, 0x44 );
n1_spi_write( 1, 0x44 );
n1_spi_write( 1, 0x55 );
n1_spi_write( 1, 0x55 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
}
{
//7)
n1_spi_write( 0, 0xB9 );
n1_spi_write( 1, 0x2C );
n1_spi_write( 1, 0x12 );
n1_spi_write( 1, 0x0C );
n1_spi_write( 1, 0x0A );
n1_spi_write( 1, 0x10 );
n1_spi_write( 1, 0x0E );
n1_spi_write( 1, 0x17 );
n1_spi_write( 1, 0x13 );
n1_spi_write( 1, 0x1F );
n1_spi_write( 1, 0x1A );
n1_spi_write( 1, 0x2A );
n1_spi_write( 1, 0x24 );
n1_spi_write( 1, 0x1F );
n1_spi_write( 1, 0x1B );
n1_spi_write( 1, 0x1A );
n1_spi_write( 1, 0x17 );
n1_spi_write( 1, 0x2B );
n1_spi_write( 1, 0x26 );
n1_spi_write( 1, 0x22 );
n1_spi_write( 1, 0x20 );
n1_spi_write( 1, 0x3A );
n1_spi_write( 1, 0x34 );
n1_spi_write( 1, 0x30 );
n1_spi_write( 1, 0x2C );
n1_spi_write( 1, 0x29 );
n1_spi_write( 1, 0x26 );
n1_spi_write( 1, 0x25 );
n1_spi_write( 1, 0x23 );
n1_spi_write( 1, 0x21 );
n1_spi_write( 1, 0x20 );
n1_spi_write( 1, 0x1E );
n1_spi_write( 1, 0x1E );
}
{
//8)
n1_spi_write( 0, 0xBA );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x00 );
n1_spi_write( 1, 0x11 );
n1_spi_write( 1, 0x22 );
n1_spi_write( 1, 0x33 );
n1_spi_write( 1, 0x44 );
n1_spi_write( 1, 0x44 );
n1_spi_write( 1, 0x44 );
n1_spi_write( 1, 0x55 );
n1_spi_write( 1, 0x55 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
n1_spi_write( 1, 0x66 );
}
}
//Sleep Out Command
{
n1_spi_write( 0, 0x11 );
}
printk("n1_panel_enable..%d\n",__LINE__);
msleep( 120 );
// muxtex_temp = 2 ;
//Display On Command
{
n1_spi_write( 0, 0x29 );
}
return 0;
}
