// Check if data is available for reading
// return:
// 0 -> no data
// 1 -> RX_DR is set or some bytes present in FIFO
uint8_t nRF24_DataReady(void) {
uint8_t status;
status = nRF24_ReadReg(nRF24_REG_STATUS);
if (status & nRF24_MASK_RX_DR) return 1;
// Checking RX_DR isn't good enough, there's can be some data in FIFO
status = nRF24_ReadReg(nRF24_REG_FIFO_STATUS);
return (status & nRF24_FIFO_RX_EMPTY) ? 0 : 1;
}
// Send data packet
// input:
// pBuf - buffer with data to send
// return:
// nRF24_MASK_MAX_RT - if transmit failed with maximum auto retransmit count
// nRF24_MAX_TX_DS - if transmit succeed
// contents of STATUS register otherwise
uint8_t nRF24_TXPacket(uint8_t * pBuf, uint8_t TX_PAYLOAD) {
uint8_t status;
CE_L();
nRF24_WriteBuf(nRF24_CMD_WREG | nRF24_REG_TX_ADDR,nRF24_TX_addr,nRF24_TX_ADDR_WIDTH); // Set static TX address
nRF24_WriteBuf(nRF24_CMD_WREG | nRF24_REG_RX_ADDR_P0,nRF24_RX_addr,nRF24_RX_ADDR_WIDTH); // Set static RX address for auto ack
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_EN_AA,0x01); // Enable auto acknowledgement for data pipe 0
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_SETUP_RETR,0x1A); // Automatic retransmission: wait 500us, 10 retries
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_RF_CH,0x6E); // Set frequency channel 110 (2.510MHz)
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_RF_SETUP,0x07); // Setup: 1Mbps, 0dBm, LNA on
nRF24_WriteBuf(nRF24_CMD_W_TX_PAYLOAD,pBuf,TX_PAYLOAD); // Write specified buffer to FIFO
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_CONFIG,0x0E); // Config: CRC on (2 bytes), Power UP, RX/TX ctl = PTX
CE_H(); // CE pin high => Start transmit
// Delay_us(10); // Must hold CE at least 10us
//while(PB_IDR_bit.IDR2 != 0); // Wait for IRQ from nRF24L01
CE_L();
status = nRF24_ReadReg(nRF24_REG_STATUS); // Read status register
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_STATUS,status | 0x70); // Clear RX_DR, TX_DS, MAX_RT flags
if (status & nRF24_MASK_MAX_RT) {
// Auto retransmit counter exceeds the programmed maximum limit. FIFO is not removed.
nRF24_RWReg(nRF24_CMD_FLUSH_TX,0xFF); // Flush TX FIFO buffer
return nRF24_MASK_MAX_RT;
};
if (status & nRF24_MASK_TX_DS) {
// Transmit ok
nRF24_RWReg(nRF24_CMD_FLUSH_TX,0xFF); // Flush TX FIFO buffer
return nRF24_MASK_TX_DS;
}
// Some banana happens
return status;
}
// Wake nRF24 from Power Down mode (usually wakes to Standby-I mode within 1.5ms)
void nRF24_Wake(void) {
uint8_t conf;
conf = nRF24_ReadReg(nRF24_REG_CONFIG);
conf |= (1<<1); // Set PWR_UP bit
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_CONFIG,conf); // Wakeup
// Delay_ms(2); // Wakeup from Power Down to Standby-I mode takes 1.5ms
}
// Put nRF24 in Power Down mode
void nRF24_PowerDown(void) {
uint8_t conf;
CE_L(); // CE pin to low
conf = nRF24_ReadReg(nRF24_REG_CONFIG);
conf &= ~(1<<1); // Clear PWR_UP bit
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_CONFIG,conf); // Go Power down mode
}
uint8_t nRF24_RXPacket(uint8_t* pBuf, uint8_t RX_PAYLOAD) {
uint8_t status;
status = nRF24_ReadReg(nRF24_REG_STATUS); // Read status register
if (status & nRF24_MASK_RX_DR) {
if ((status & 0x0E) == 0) {
// pipe 0
nRF24_ReadBuf(nRF24_CMD_R_RX_PAYLOAD,pBuf,RX_PAYLOAD); // read received payload from RX FIFO buffer
}
nRF24_ReadWrite(nRF24_CMD_FLUSH_RX); // Flush RX FIFO buffer
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_STATUS,status | 0x70); // Clear RX_DR, TX_DS, MAX_RT flags
//return nRF24_MASK_RX_DR;
return status;
}
// Some banana happens
nRF24_ReadWrite(nRF24_CMD_FLUSH_RX); // Flush RX FIFO buffer
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_STATUS,status | 0x70); // Clear RX_DR, TX_DS, MAX_RT flags
return status;
}
// Clear all IRQ flags
void nRF24_ClearIRQFlags(void) {
uint8_t status;
status = nRF24_ReadReg(nRF24_REG_STATUS);
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_STATUS,status | 0x70); // Clear RX_DR, TX_DS, MAX_RT flags
}