static void decode_mc4_mce(struct mce *m) { struct cpuinfo_x86 *c = &boot_cpu_data; int node_id = amd_get_nb_id(m->extcpu); u16 ec = EC(m->status); u8 xec = XEC(m->status, 0x1f); u8 offset = 0; pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id); switch (xec) { case 0x0 ... 0xe: /* special handling for DRAM ECCs */ if (xec == 0x0 || xec == 0x8) { /* no ECCs on F11h */ if (c->x86 == 0x11) goto wrong_mc4_mce; pr_cont("%s.\n", mc4_mce_desc[xec]); if (nb_bus_decoder) nb_bus_decoder(node_id, m); return; } break; case 0xf: if (TLB_ERROR(ec)) pr_cont("GART Table Walk data error.\n"); else if (BUS_ERROR(ec)) pr_cont("DMA Exclusion Vector Table Walk error.\n"); else goto wrong_mc4_mce; return; case 0x19: if (boot_cpu_data.x86 == 0x15) pr_cont("Compute Unit Data Error.\n"); else goto wrong_mc4_mce; return; case 0x1c ... 0x1f: offset = 13; break; default: goto wrong_mc4_mce; } pr_cont("%s.\n", mc4_mce_desc[xec - offset]); return; wrong_mc4_mce: pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n"); }
void amd_decode_nb_mce(struct mce *m) { struct cpuinfo_x86 *c = &boot_cpu_data; int node_id = amd_get_nb_id(m->extcpu); u16 ec = EC(m->status); u8 xec = XEC(m->status, 0x1f); pr_emerg(HW_ERR "Northbridge Error (node %d): ", node_id); switch (xec) { case 0x2: pr_cont("Sync error (sync packets on HT link detected).\n"); return; case 0x3: pr_cont("HT Master abort.\n"); return; case 0x4: pr_cont("HT Target abort.\n"); return; case 0x7: pr_cont("NB Watchdog timeout.\n"); return; case 0x9: pr_cont("SVM DMA Exclusion Vector error.\n"); return; default: break; } if (!fam_ops->nb_mce(ec, xec)) goto wrong_nb_mce; if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x15) if ((xec == 0x8 || xec == 0x0) && nb_bus_decoder) nb_bus_decoder(node_id, m); return; wrong_nb_mce: pr_emerg(HW_ERR "Corrupted NB MCE info?\n"); }
void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg) { struct cpuinfo_x86 *c = &boot_cpu_data; u16 ec = EC(m->status); u8 xec = XEC(m->status, 0x1f); u32 nbsh = (u32)(m->status >> 32); int core = -1; pr_emerg(HW_ERR "Northbridge Error (node %d", node_id); /* F10h, revD can disable ErrCpu[3:0] through ErrCpuVal */ if (c->x86 == 0x10 && c->x86_model > 7) { if (nbsh & NBSH_ERR_CPU_VAL) core = nbsh & nb_err_cpumask; } else { u8 assoc_cpus = nbsh & nb_err_cpumask; if (assoc_cpus > 0) core = fls(assoc_cpus) - 1; } if (core >= 0) pr_cont(", core %d): ", core); else pr_cont("): "); switch (xec) { case 0x2: pr_cont("Sync error (sync packets on HT link detected).\n"); return; case 0x3: pr_cont("HT Master abort.\n"); return; case 0x4: pr_cont("HT Target abort.\n"); return; case 0x7: pr_cont("NB Watchdog timeout.\n"); return; case 0x9: pr_cont("SVM DMA Exclusion Vector error.\n"); return; default: break; } if (!fam_ops->nb_mce(ec, xec)) goto wrong_nb_mce; if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x15) if ((xec == 0x8 || xec == 0x0) && nb_bus_decoder) nb_bus_decoder(node_id, m, nbcfg); return; wrong_nb_mce: pr_emerg(HW_ERR "Corrupted NB MCE info?\n"); }