static void nile4_irq_setup(void) { int i; /* Map all interrupts to CPU int #0 (IP2) */ nile4_map_irq_all(0); /* PCI INTA#-E# must be level triggered */ nile4_set_pci_irq_level_or_edge(0, 1); nile4_set_pci_irq_level_or_edge(1, 1); nile4_set_pci_irq_level_or_edge(2, 1); nile4_set_pci_irq_level_or_edge(3, 1); /* PCI INTA#, B#, D# must be active low, INTC# must be active high */ nile4_set_pci_irq_polarity(0, 0); nile4_set_pci_irq_polarity(1, 0); nile4_set_pci_irq_polarity(2, 1); nile4_set_pci_irq_polarity(3, 0); for (i = 0; i < 16; i++) nile4_clear_irq(i); /* Enable CPU int #0 */ nile4_enable_irq_output(0); /* memory resource acquire in ddb_setup */ }
static void nile4_irq_setup(void) { int i; /* Map all interrupts to CPU int #0 */ nile4_map_irq_all(0); /* PCI INTA#-E# must be level triggered */ nile4_set_pci_irq_level_or_edge(0, 1); nile4_set_pci_irq_level_or_edge(1, 1); nile4_set_pci_irq_level_or_edge(2, 1); nile4_set_pci_irq_level_or_edge(3, 1); nile4_set_pci_irq_level_or_edge(4, 1); /* PCI INTA#-D# must be active low, INTE# must be active high */ nile4_set_pci_irq_polarity(0, 0); nile4_set_pci_irq_polarity(1, 0); nile4_set_pci_irq_polarity(2, 0); nile4_set_pci_irq_polarity(3, 0); nile4_set_pci_irq_polarity(4, 1); for (i = 0; i < 16; i++) nile4_clear_irq(i); /* Enable CPU int #0 */ nile4_enable_irq_output(0); request_mem_region(NILE4_BASE, NILE4_SIZE, "Nile 4"); }