static bool
dead_cf_block(nir_block *block)
{
nir_if *following_if = nir_block_get_following_if(block);
if (following_if) {
nir_const_value *const_value =
nir_src_as_const_value(following_if->condition);
if (!const_value)
return false;
opt_constant_if(following_if, const_value->u[0] != 0);
return true;
}
nir_loop *following_loop = nir_block_get_following_loop(block);
if (!following_loop)
return false;
if (!loop_is_dead(following_loop))
return false;
nir_cf_node_remove(&following_loop->cf_node);
return true;
}
nir_foreach_instr(instr, block) {
if (instr->type != nir_instr_type_tex)
continue;
nir_tex_instr *tex = nir_instr_as_tex(instr);
int plane_index = nir_tex_instr_src_index(tex, nir_tex_src_plane);
if (plane_index < 0)
continue;
nir_const_value *plane = nir_src_as_const_value(tex->src[plane_index].src);
assume(plane);
if (plane->i32[0] > 0) {
unsigned y_samp = tex->texture_index;
assume(tex->texture_index == tex->sampler_index);
assume(((state->lower_3plane & (1 << y_samp)) && plane->i32[0] < 3) ||
(plane->i32[0] < 2));
tex->texture_index = tex->sampler_index =
state->sampler_map[y_samp][plane->i32[0] - 1];
}
nir_tex_instr_remove_src(tex, plane_index);
}
static bool
deref_has_indirect(nir_deref_instr *deref)
{
while (deref->deref_type != nir_deref_type_var) {
if (deref->deref_type == nir_deref_type_array &&
nir_src_as_const_value(deref->arr.index) == NULL)
return true;
deref = nir_deref_instr_parent(deref);
}
return false;
}
static nir_src
get_deref_reg_src(nir_deref_instr *deref, struct locals_to_regs_state *state)
{
nir_builder *b = &state->builder;
nir_src src;
src.is_ssa = false;
src.reg.reg = get_reg_for_deref(deref, state);
src.reg.base_offset = 0;
src.reg.indirect = NULL;
/* It is possible for a user to create a shader that has an array with a
* single element and then proceed to access it indirectly. Indirectly
* accessing a non-array register is not allowed in NIR. In order to
* handle this case we just convert it to a direct reference.
*/
if (src.reg.reg->num_array_elems == 0)
return src;
unsigned inner_array_size = 1;
for (const nir_deref_instr *d = deref; d; d = nir_deref_instr_parent(d)) {
if (d->deref_type != nir_deref_type_array)
continue;
nir_const_value *const_index = nir_src_as_const_value(d->arr.index);
if (const_index && !src.reg.indirect) {
src.reg.base_offset += const_index->u32[0] * inner_array_size;
} else {
if (src.reg.indirect) {
assert(src.reg.base_offset == 0);
} else {
src.reg.indirect = ralloc(b->shader, nir_src);
*src.reg.indirect =
nir_src_for_ssa(nir_imm_int(b, src.reg.base_offset));
src.reg.base_offset = 0;
}
assert(src.reg.indirect->is_ssa);
src.reg.indirect->ssa =
nir_iadd(b, src.reg.indirect->ssa,
nir_imul(b, nir_ssa_for_src(b, d->arr.index, 1),
nir_imm_int(b, inner_array_size)));
}
inner_array_size *= glsl_get_length(nir_deref_instr_parent(d)->type);
}
return src;
}
nir_foreach_instr_safe(instr, block) {
if (instr->type != nir_instr_type_intrinsic)
continue;
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
if ((mode == nir_var_shader_in && is_input(intrin)) ||
(mode == nir_var_shader_out && is_output(intrin))) {
nir_src *offset = nir_get_io_offset_src(intrin);
nir_const_value *const_offset = nir_src_as_const_value(*offset);
if (const_offset) {
intrin->const_index[0] += const_offset->u32[0];
b->cursor = nir_before_instr(&intrin->instr);
nir_instr_rewrite_src(&intrin->instr, offset,
nir_src_for_ssa(nir_imm_int(b, 0)));
}
}
}
void
vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
{
dst_reg dest;
src_reg src;
switch (instr->intrinsic) {
case nir_intrinsic_load_per_vertex_input: {
/* The EmitNoIndirectInput flag guarantees our vertex index will
* be constant. We should handle indirects someday.
*/
nir_const_value *vertex = nir_src_as_const_value(instr->src[0]);
nir_const_value *offset = nir_src_as_const_value(instr->src[1]);
/* Make up a type...we have no way of knowing... */
const glsl_type *const type = glsl_type::ivec(instr->num_components);
src = src_reg(ATTR, BRW_VARYING_SLOT_COUNT * vertex->u32[0] +
instr->const_index[0] + offset->u32[0],
type);
/* gl_PointSize is passed in the .w component of the VUE header */
if (instr->const_index[0] == VARYING_SLOT_PSIZ)
src.swizzle = BRW_SWIZZLE_WWWW;
dest = get_nir_dest(instr->dest, src.type);
dest.writemask = brw_writemask_for_size(instr->num_components);
emit(MOV(dest, src));
break;
}
case nir_intrinsic_load_input:
unreachable("nir_lower_io should have produced per_vertex intrinsics");
case nir_intrinsic_emit_vertex_with_counter: {
this->vertex_count =
retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD);
int stream_id = instr->const_index[0];
gs_emit_vertex(stream_id);
break;
}
case nir_intrinsic_end_primitive_with_counter:
this->vertex_count =
retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD);
gs_end_primitive();
break;
case nir_intrinsic_set_vertex_count:
this->vertex_count =
retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD);
break;
case nir_intrinsic_load_primitive_id:
assert(gs_prog_data->include_primitive_id);
dest = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
emit(MOV(dest, retype(brw_vec4_grf(1, 0), BRW_REGISTER_TYPE_D)));
break;
case nir_intrinsic_load_invocation_id: {
src_reg invocation_id =
src_reg(nir_system_values[SYSTEM_VALUE_INVOCATION_ID]);
assert(invocation_id.file != BAD_FILE);
dest = get_nir_dest(instr->dest, invocation_id.type);
emit(MOV(dest, invocation_id));
break;
}
default:
vec4_visitor::nir_emit_intrinsic(instr);
}
}
void
vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
{
switch (instr->intrinsic) {
case nir_intrinsic_load_invocation_id:
emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD),
invocation_id));
break;
case nir_intrinsic_load_primitive_id:
emit(TCS_OPCODE_GET_PRIMITIVE_ID,
get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
break;
case nir_intrinsic_load_patch_vertices_in:
emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
brw_imm_d(key->input_vertices)));
break;
case nir_intrinsic_load_per_vertex_input: {
src_reg indirect_offset = get_indirect_offset(instr);
unsigned imm_offset = instr->const_index[0];
nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]);
src_reg vertex_index =
vertex_const ? src_reg(brw_imm_ud(vertex_const->u32[0]))
: get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1);
dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
dst.writemask = brw_writemask_for_size(instr->num_components);
emit_input_urb_read(dst, vertex_index, imm_offset,
nir_intrinsic_component(instr), indirect_offset);
break;
}
case nir_intrinsic_load_input:
unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
break;
case nir_intrinsic_load_output:
case nir_intrinsic_load_per_vertex_output: {
src_reg indirect_offset = get_indirect_offset(instr);
unsigned imm_offset = instr->const_index[0];
dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
dst.writemask = brw_writemask_for_size(instr->num_components);
if (imm_offset == 0 && indirect_offset.file == BAD_FILE) {
dst.type = BRW_REGISTER_TYPE_F;
/* This is a read of gl_TessLevelInner[], which lives in the
* Patch URB header. The layout depends on the domain.
*/
switch (key->tes_primitive_mode) {
case GL_QUADS: {
/* DWords 3-2 (reversed); use offset 0 and WZYX swizzle. */
dst_reg tmp(this, glsl_type::vec4_type);
emit_output_urb_read(tmp, 0, 0, src_reg());
emit(MOV(writemask(dst, WRITEMASK_XY),
swizzle(src_reg(tmp), BRW_SWIZZLE_WZYX)));
break;
}
case GL_TRIANGLES:
/* DWord 4; use offset 1 but normal swizzle/writemask. */
emit_output_urb_read(writemask(dst, WRITEMASK_X), 1, 0,
src_reg());
break;
case GL_ISOLINES:
/* All channels are undefined. */
return;
default:
unreachable("Bogus tessellation domain");
}
} else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
dst.type = BRW_REGISTER_TYPE_F;
unsigned swiz = BRW_SWIZZLE_WZYX;
/* This is a read of gl_TessLevelOuter[], which lives in the
* high 4 DWords of the Patch URB header, in reverse order.
*/
switch (key->tes_primitive_mode) {
case GL_QUADS:
dst.writemask = WRITEMASK_XYZW;
break;
case GL_TRIANGLES:
dst.writemask = WRITEMASK_XYZ;
break;
case GL_ISOLINES:
/* Isolines are not reversed; swizzle .zw -> .xy */
swiz = BRW_SWIZZLE_ZWZW;
dst.writemask = WRITEMASK_XY;
return;
default:
unreachable("Bogus tessellation domain");
}
dst_reg tmp(this, glsl_type::vec4_type);
emit_output_urb_read(tmp, 1, 0, src_reg());
emit(MOV(dst, swizzle(src_reg(tmp), swiz)));
} else {
emit_output_urb_read(dst, imm_offset, nir_intrinsic_component(instr),
indirect_offset);
}
break;
}
case nir_intrinsic_store_output:
case nir_intrinsic_store_per_vertex_output: {
src_reg value = get_nir_src(instr->src[0]);
unsigned mask = instr->const_index[1];
unsigned swiz = BRW_SWIZZLE_XYZW;
src_reg indirect_offset = get_indirect_offset(instr);
unsigned imm_offset = instr->const_index[0];
/* The passthrough shader writes the whole patch header as two vec4s;
* skip all the gl_TessLevelInner/Outer swizzling.
*/
if (indirect_offset.file == BAD_FILE && !is_passthrough_shader) {
if (imm_offset == 0) {
value.type = BRW_REGISTER_TYPE_F;
mask &=
(1 << tesslevel_inner_components(key->tes_primitive_mode)) - 1;
/* This is a write to gl_TessLevelInner[], which lives in the
* Patch URB header. The layout depends on the domain.
*/
switch (key->tes_primitive_mode) {
case GL_QUADS:
/* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
* We use an XXYX swizzle to reverse put .xy in the .wz
* channels, and use a .zw writemask.
*/
swiz = BRW_SWIZZLE4(0, 0, 1, 0);
mask = writemask_for_backwards_vector(mask);
break;
case GL_TRIANGLES:
/* gl_TessLevelInner[].x lives at DWord 4, so we set the
* writemask to X and bump the URB offset by 1.
*/
imm_offset = 1;
break;
case GL_ISOLINES:
/* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
return;
default:
unreachable("Bogus tessellation domain");
}
} else if (imm_offset == 1) {
value.type = BRW_REGISTER_TYPE_F;
mask &=
(1 << tesslevel_outer_components(key->tes_primitive_mode)) - 1;
/* This is a write to gl_TessLevelOuter[] which lives in the
* Patch URB Header at DWords 4-7. However, it's reversed, so
* instead of .xyzw we have .wzyx.
*/
if (key->tes_primitive_mode == GL_ISOLINES) {
/* Isolines .xy should be stored in .zw, in order. */
swiz = BRW_SWIZZLE4(0, 0, 0, 1);
mask <<= 2;
} else {
/* Other domains are reversed; store .wzyx instead of .xyzw. */
swiz = BRW_SWIZZLE_WZYX;
mask = writemask_for_backwards_vector(mask);
}
}
}
unsigned first_component = nir_intrinsic_component(instr);
if (first_component) {
assert(swiz == BRW_SWIZZLE_XYZW);
swiz = BRW_SWZ_COMP_OUTPUT(first_component);
mask = mask << first_component;
}
emit_urb_write(swizzle(value, swiz), mask,
imm_offset, indirect_offset);
break;
}
case nir_intrinsic_barrier: {
dst_reg header = dst_reg(this, glsl_type::uvec4_type);
emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
break;
}
default:
vec4_visitor::nir_emit_intrinsic(instr);
}
}
