static void prog_pll(struct drm_device *dev, struct nv04_pm_clock *clk) { struct drm_nouveau_private *dev_priv = dev->dev_private; u32 reg = clk->pll.reg; /* thank the insane nouveau_hw_setpll() interface for this */ if (dev_priv->card_type >= NV_40) reg += 4; nouveau_hw_setpll(dev, reg, &clk->calc); }
void nv04_pm_clock_set(struct drm_device *dev, void *pre_state) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nv04_pm_state *state = pre_state; u32 reg = state->pll.reg; /* thank the insane nouveau_hw_setpll() interface for this */ if (dev_priv->card_type >= NV_40) reg += 4; nouveau_hw_setpll(dev, reg, &state->calc); kfree(state); }
void nv04_pm_clock_set(struct drm_device *dev, void *pre_state) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nv04_pm_state *state = pre_state; u32 reg = state->pll.reg; /* thank the insane nouveau_hw_setpll() interface for this */ if (dev_priv->card_type >= NV_40) reg += 4; nouveau_hw_setpll(dev, reg, &state->calc); if (dev_priv->card_type < NV_30 && reg == NV_PRAMDAC_MPLL_COEFF) { if (dev_priv->card_type == NV_20) nv_mask(dev, 0x1002c4, 0, 1 << 20); /* Reset the DLLs */ nv_mask(dev, 0x1002c0, 0, 1 << 8); } kfree(state); }