void mainboard_config_superio(void) { const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); /* Select HWM/LED functions instead of floppy functions. */ pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); /* Power RAM in S3 and let the PCH handle power failure actions. */ pnp_set_logical_device(ACPI_DEV); pnp_write_config(ACPI_DEV, 0xe4, 0x70); /* * Don't know what's needed here, just set the same as the vendor * firmware. */ pnp_set_logical_device(IR_DEV); pnp_write_config(IR_DEV, 0xf1, 0x5c); nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x42); agesawrapper_amdinitenv(); amd_initenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
static void mb_lpc_setup(void) { u32 reg32; /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&mainboard_gpio_map); /* Set GPIOs on superio, enable UART */ if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776)) { nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); pnp_set_logical_device(SERIAL_DEV_R2); pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80); pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80); pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60); nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2); nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE); } else { winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE); } /* IRQ routing */ RCBA16(D31IR) = 0x0132; RCBA16(D29IR) = 0x0237; /* Enable IOAPIC */ RCBA8(OIC) = 0x03; RCBA8(OIC); reg32 = RCBA32(GCS); reg32 |= (1 << 5); RCBA32(GCS) = reg32; RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD | FD_ACAUD | 1; RCBA32(CG) = 0x00000001; }
void car_mainboard_pre_console_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); }