/* (Called from exc.S with global interrupts disabled.) */
void __error(int num) {
nvic_globalirq_enable();
usart_putstr(ERROR_USART, "\r\nexception: ");
usart_putudec(ERROR_USART, num);
usart_putc(ERROR_USART, '\n');
usart_putc(ERROR_USART, '\r');
for(;;);
throb();
/* Turn off peripheral interrupts */
nvic_irq_disable_all();
/* Turn off timers */
timer_disable_all();
/* Turn off ADC */
adc_disable_all();
/* Turn off all USARTs */
usart_disable_all();
/* Turn the USB interrupt back on so the bootloader keeps on functioning */
nvic_irq_enable(NVIC_USB_HP_CAN_TX);
nvic_irq_enable(NVIC_USB_LP_CAN_RX0);
/* Reenable global interrupts */
nvic_globalirq_enable();
throb();
}
/**
* @brief Attach a RTC interrupt.
* @param interrupt Interrupt number to attach to; this may be any rtc_interrupt_id.
* @param handler Handler to attach to the given interrupt.
* @see rtc_interrupt_id
*/
void rtc_attach_interrupt( uint8 interrupt,
voidFuncPtr handler) {
RTC->handlers[interrupt] = handler;
rtc_enable_irq(interrupt);
switch (interrupt) {
case RTC_SECONDS_INTERRUPT: nvic_irq_enable(NVIC_RTC); break;
case RTC_OVERFLOW_INTERRUPT: nvic_irq_enable(NVIC_RTC); break;
case RTC_ALARM_GLOBAL_INTERRUPT: nvic_irq_enable(NVIC_RTC); break;
case RTC_ALARM_SPECIFIC_INTERRUPT: nvic_irq_enable(NVIC_RTCALARM); break; // The alarm specific interrupt can wake us from deep sleep.
}
}
/*!
\brief configure the nested vectored interrupt controller
\param[in] none
\param[out] none
\retval none
*/
void nvic_config(void)
{
#ifdef CAN0_USED
/* configure CAN0 NVIC */
nvic_irq_enable(CAN0_RX0_IRQn,0,0);
#else
/* configure CAN1 NVIC */
nvic_irq_enable(CAN1_RX0_IRQn,0,0);
#endif
}
/**
* @brief Initialize an I2C device as bus master
* @param dev Device to enable
* @param flags Bitwise or of the following I2C options:
* I2C_FAST_MODE: 400 khz operation,
* I2C_DUTY_16_9: 16/9 Tlow/Thigh duty cycle (only applicable for
* fast mode),
* I2C_BUS_RESET: Reset the bus and clock out any hung slaves on
* initialization,
* I2C_10BIT_ADDRESSING: Enable 10-bit addressing,
* I2C_REMAP: (deprecated, STM32F1 only) Remap I2C1 to SCL/PB8
* SDA/PB9.
*/
void i2c_master_enable(i2c_dev *dev, uint32 flags) {
/* Reset the bus. Clock out any hung slaves. */
if (flags & I2C_BUS_RESET) {
fooprint("i2c_master_enable: calling i2c_bus_reset");
i2c_bus_reset(dev);
}
fooprint("i2c_master_enable: entry");
/* PE must be disabled to configure the device */
// ASSERT(!(dev->regs->CR1 & I2C_CR1_PE));
/* Ugh */
//_i2c_handle_remap(dev, flags);
fooprint("i2c_master_enable: calling i2c_init");
/* Turn on clock and set GPIO modes */
i2c_init(dev);
fooprint("i2c_master_enable: calling i2c_config_gpios");
i2c_config_gpios(dev);
fooprint("i2c_master_enable: calling set_freq_scl");
/* Configure clock and rise time */
set_freq_scl(dev, flags);
fooprint("i2c_master_enable: calling nvic_irq_enable(ev)");
/* Enable event and buffer interrupts */
nvic_irq_enable(dev->ev_nvic_line);
fooprint("i2c_master_enable: calling nvic_irq_enable(er)");
nvic_irq_enable(dev->er_nvic_line);
//gutted
fooprint("i2c_master_enable: calling i2c_enable_irq");
i2c_enable_irq(dev, I2C_CFGR_STOIEN_MASK | I2C_CFGR_ACKIEN_MASK | I2C_CFGR_RXIEN_MASK | I2C_CFGR_TXIEN_MASK | I2C_CFGR_STAIEN_MASK | I2C_CFGR_ARBLIEN_MASK);
/* Make it go! */
fooprint("i2c_master_enable: calling i2c_peripheral_enable");
//gutted
i2c_peripheral_enable(dev);
dev->state = I2C_STATE_IDLE;
fooprint("i2c_master_enable: exit, dev-state = I2C_STATE_IDLE");
}
void DMA_init(void) {
dma_init(DMA1);
// TIM2 Update event
/* DMA1 Channel2 configuration ----------------------------------------------*/
dma_setup_transfer(DMA1, DMA_CH2, (volatile void*) &(GPIOA->regs->ODR), DMA_SIZE_32BITS,
(volatile void*) &(WS2812_IO_High), DMA_SIZE_8BITS, DMA_FROM_MEM);
dma_set_priority(DMA1, DMA_CH2, DMA_PRIORITY_HIGH);
// TIM2 CC1 event
/* DMA1 Channel5 configuration ----------------------------------------------*/
dma_setup_transfer(DMA1, DMA_CH5, (volatile void*) &(GPIOA->regs->ODR), DMA_SIZE_32BITS,
(volatile void*) WS2812_buffer, DMA_SIZE_8BITS, DMA_FROM_MEM | DMA_MINC_MODE);
dma_set_priority(DMA1, DMA_CH5, DMA_PRIORITY_HIGH);
// TIM2 CC2 event
/* DMA1 Channel7 configuration ----------------------------------------------*/
dma_setup_transfer(DMA1, DMA_CH7, (volatile void*) &(GPIOA->regs->ODR), DMA_SIZE_32BITS,
(volatile void*) &(WS2812_IO_Low), DMA_SIZE_8BITS, DMA_FROM_MEM | DMA_TRNS_CMPLT);
dma_set_priority(DMA1, DMA_CH7, DMA_PRIORITY_HIGH);
/* configure DMA1 Channel7 interrupt */
nvic_irq_set_priority(NVIC_DMA_CH7, 1);
nvic_irq_enable(NVIC_DMA_CH7);
dma_attach_interrupt(DMA1, DMA_CH7, DMA1_Channel7_IRQHandler);
/* enable DMA1 Channel7 transfer complete interrupt */
}
/**
* @brief Initialize a serial port.
* @param dev Serial port to be initialized
*/
void usart_init(usart_dev *dev, uint8_t *buff, uint16 buff_size) {
usart_reg_map *regs = dev->regs;
rb_init(dev->rb, buff_size, buff);
// Clocking must be enabled to modify registers
clk_enable_dev(dev->clk_id);
// Configuration: 8-bit, 1stop, no-parity
// tx configuration
REG_SET_CLR(regs->CONFIG, 0,
UART_CFGR_TDATLN_MASK | UART_CFGR_TPAREN_MASK | UART_CFGR_TSTPMD_MASK | UART_CFGR_TINVEN_MASK);
REG_SET_CLR(regs->CONFIG, 1,
UART_CFGR_TDATLN_8_BITS | UART_CFGR_TSTRTEN_EN | UART_CFGR_TSTPEN_EN | (1 << UART_CFGR_TSTPMD_BIT));
// rx configuration
REG_SET_CLR(regs->CONFIG, 0,
UART_CFGR_RDATLN_MASK | UART_CFGR_RSTPMD_MASK | UART_CFGR_RINVEN_MASK);
REG_SET_CLR(regs->CONFIG, 1,
UART_CFGR_RDATLN_8_BITS | UART_CFGR_RSTRTEN_EN | UART_CFGR_RSTPEN_EN | (1 << UART_CFGR_RSTPMD_BIT));
// Interrupt when a single byte is in rx buffer
REG_SET_CLR(regs->FIFOCN, 0 , 0x00000030);
// Enable IRQ on NVIC
nvic_clr_pending_irq(dev->irq_num);
nvic_irq_enable(dev->irq_num);
}
/*!
\brief configure comparator
\param[in] none
\param[out] none
\retval none
*/
void cmp_config(void)
{
/* enable GPIOA clock */
rcu_periph_clock_enable(RCU_GPIOA);
/* configure PA1 as comparator input */
gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_1);
gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_1);
/* enable comparator clock */
rcu_periph_clock_enable(RCU_CFGCMP);
/* configure comparator channel0 */
cmp_mode_init(CMP_CHANNEL_CMP0, CMP_LOWSPEED, CMP_VREFINT, CMP_HYSTERESIS_HIGH);
cmp_output_init(CMP_CHANNEL_CMP0, CMP_OUTPUT_NONE, CMP_OUTPUT_POLARITY_NOINVERTED);
/* configure comparator channel1 */
cmp_mode_init(CMP_CHANNEL_CMP1, CMP_LOWSPEED, CMP_1_2VREFINT, CMP_HYSTERESIS_HIGH);
cmp_output_init(CMP_CHANNEL_CMP1, CMP_OUTPUT_NONE, CMP_OUTPUT_POLARITY_NOINVERTED);
/* configure exti line */
exti_init(EXTI_21, EXTI_INTERRUPT, EXTI_TRIG_BOTH);
exti_init(EXTI_22, EXTI_INTERRUPT, EXTI_TRIG_BOTH);
/* configure ADC_CMP nvic */
nvic_irq_enable(ADC_CMP_IRQn, 0, 0);
/* enable comparator window */
cmp_window_enable();
/* enable comparator channels */
cmp_channel_enable(CMP_CHANNEL_CMP0);
cmp_channel_enable(CMP_CHANNEL_CMP1);
}
void
usart_init(usart_num num)
{
if(!usart_available(num))
return;
usart_driver *driver = &usart_drivers[num];
const usart_dev *dev = usart_get_dev(num);
rcc_clk_enable(dev->clk_id);
nvic_irq_enable(dev->irq);
/* initial driver */
driver->p_dev = dev;
/* enable receive and transmit mode */
usart_t *usart = (usart_t *)dev->reg;
usart->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE | USART_CR1_IDLEIE;
/* Parity: none, stop bit: 0, flow control: none */
usart->CR2 = 0;
/* Enable TX/RX DMA */
usart->CR3 = 0;
(void)usart->SR;
(void)usart->DR;
/* Initial DMA */
usart_dma_init(num);
usart_set_used(num);
}
/*!
\brief configure the CEC peripheral
\param[in] none
\param[out] none
\retval none
*/
void cec_config(void)
{
/* enable clocks */
rcu_periph_clock_enable(RCU_GPIOB);
rcu_periph_clock_enable(RCU_CEC);
/* configure CEC_LINE_GPIO as output open drain */
gpio_mode_set(GPIOB,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_8);
gpio_output_options_set(GPIOB,GPIO_OTYPE_OD,GPIO_OSPEED_50MHZ,GPIO_PIN_8);
gpio_af_set(GPIOB,GPIO_AF_0,GPIO_PIN_8);
/* configure priority group */
nvic_priority_group_set(NVIC_PRIGROUP_PRE1_SUB3);
/* enable the CEC global interrupt (with higher priority) */
nvic_irq_enable(CEC_IRQn,0,0);
/* configure CEC */
cec_init(CEC_SFT_START_SOM,CEC_SFT_1POINT5_PERIOD,CEC_OWN_ADDRESS2);
cec_error_config(CEC_BROADCAST_ERROR_BIT_OFF,CEC_LONG_PERIOD_ERROR_BIT_OFF,CEC_RISING_PERIOD_ERROR_BIT_OFF,CEC_STOP_RISING_ERROR_BIT_OFF);
cec_reception_tolerance_disable();
/* activate CEC interrupts associated to the set of TX and RX flags */
cec_interrupt_enable(CEC_INTEN_TENDIE | CEC_INTEN_TBRIE | CEC_INTEN_RENDIE | CEC_INTEN_RBRIE);
/* activate CEC interrupts associated to the set of TX and RX error */
cec_interrupt_enable(CEC_INTEN_ROIE | CEC_INTEN_RBREIE | CEC_INTEN_RSBPEIE | CEC_INTEN_RLBPEIE
| CEC_INTEN_RAEIE | CEC_INTEN_LSTARBIE | CEC_INTEN_TUIE | CEC_INTEN_TERRIE | CEC_INTEN_TAERRIE );
/* enable CEC */
cec_enable();
}
void TIM2_init() {
uint32_t SystemCoreClock = 72000000;
uint16_t prescalerValue = (uint16_t) (SystemCoreClock / 24000000) - 1;
rcc_clk_enable(RCC_TIMER2);
/* Time base configuration */
timer_pause(TIMER2);
timer_set_prescaler(TIMER2, prescalerValue);
timer_set_reload(TIMER2, 29); // 800kHz
/* Timing Mode configuration: Channel 1 */
timer_set_mode(TIMER2, 1, TIMER_OUTPUT_COMPARE);
timer_set_compare(TIMER2, 1, 8);
timer_oc_set_mode(TIMER2, 1, TIMER_OC_MODE_FROZEN, ~TIMER_OC_PE);
/* Timing Mode configuration: Channel 2 */
timer_set_mode(TIMER2, 2, TIMER_OUTPUT_COMPARE);
timer_set_compare(TIMER2, 2, 17);
timer_oc_set_mode(TIMER2, 2, TIMER_OC_MODE_PWM_1, ~TIMER_OC_PE);
//timer_resume(TIMER2);
timer_attach_interrupt(TIMER2, TIMER_UPDATE_INTERRUPT, TIM2_IRQHandler);
/* configure TIM2 interrupt */
nvic_irq_set_priority(NVIC_TIMER2, 2);
nvic_irq_enable(NVIC_TIMER2);
}
/* Advanced control timers have several IRQ lines corresponding to
* different timer interrupts.
*
* Note: This function assumes that the only advanced timers are TIM1
* and TIM8, and needs the obvious changes if that assumption is
* violated by a later STM32 series. */
static void enable_adv_irq(timer_dev *dev, timer_interrupt_id id) {
uint8 is_tim1 = dev->clk_id == RCC_TIMER1;
nvic_irq_num irq_num;
switch (id) {
case TIMER_UPDATE_INTERRUPT:
irq_num = (is_tim1 ?
NVIC_TIMER1_UP_TIMER10 :
NVIC_TIMER8_UP_TIMER13);
break;
case TIMER_CC1_INTERRUPT: /* Fall through */
case TIMER_CC2_INTERRUPT: /* ... */
case TIMER_CC3_INTERRUPT: /* ... */
case TIMER_CC4_INTERRUPT:
irq_num = is_tim1 ? NVIC_TIMER1_CC : NVIC_TIMER8_CC;
break;
case TIMER_COM_INTERRUPT: /* Fall through */
case TIMER_TRG_INTERRUPT:
irq_num = (is_tim1 ?
NVIC_TIMER1_TRG_COM_TIMER11 :
NVIC_TIMER8_TRG_COM_TIMER14);
break;
case TIMER_BREAK_INTERRUPT:
irq_num = (is_tim1 ?
NVIC_TIMER1_BRK_TIMER9 :
NVIC_TIMER8_BRK_TIMER12);
break;
default:
/* Can't happen, but placate the compiler */
ASSERT(0);
return;
}
nvic_irq_enable(irq_num);
}
/*!
\brief configure interrupt priority
\param[in] none
\param[out] none
\retval none
*/
void nvic_config(void)
{
/* 1 bit for pre-emption priority, 3 bits for subpriority */
nvic_priority_group_set(NVIC_PRIGROUP_PRE1_SUB3);
/* enable the USB low priority interrupt */
nvic_irq_enable(USBD_LP_IRQn, 1, 0);
}
/**
* @brief Attaches an interrupt handler for the CAN peripheral
*
* Attaches an interrupt handler for the CAN peripheral.
* Note: for the RX handler, this must be called after disabling USB
*/
void can_attach_interrupt(can_dev* const dev, can_interrupt_type interrupt_type, void (*handler)(void)) {
switch (interrupt_type) {
case CAN_INT_TX:
dev->tx_handler = handler;
nvic_irq_enable(dev->tx_irq_num);
break;
case CAN_INT_RX:
dev->rx_handler = handler;
nvic_irq_enable(dev->rx_irq_num);
break;
case CAN_INT_SC:
dev->sc_handler = handler;
nvic_irq_enable(dev->sc_irq_num);
break;
default:
return;
}
}
/**
* @brief Initialize an I2C device as bus master
* @param dev Device to enable
* @param flags Bitwise or of the following I2C options:
* I2C_FAST_MODE: 400 khz operation,
* I2C_DUTY_16_9: 16/9 Tlow/Thigh duty cycle (only applicable for
* fast mode),
* I2C_BUS_RESET: Reset the bus and clock out any hung slaves on
* initialization,
* I2C_10BIT_ADDRESSING: Enable 10-bit addressing,
* I2C_REMAP: (deprecated, STM32F1 only) Remap I2C1 to SCL/PB8
* SDA/PB9.
*/
void i2c_master_enable(i2c_dev *dev, uint32 flags) {
/* PE must be disabled to configure the device */
ASSERT(!(dev->regs->CR1 & I2C_CR1_PE));
/* Ugh */
_i2c_handle_remap(dev, flags);
/* Reset the bus. Clock out any hung slaves. */
if (flags & I2C_BUS_RESET) {
i2c_bus_reset(dev);
}
/* Turn on clock and set GPIO modes */
i2c_init(dev);
i2c_config_gpios(dev);
/* Configure clock and rise time */
set_ccr_trise(dev, flags);
/* Enable event and buffer interrupts */
nvic_irq_enable(dev->ev_nvic_line);
nvic_irq_enable(dev->er_nvic_line);
i2c_enable_irq(dev, I2C_IRQ_EVENT | I2C_IRQ_BUFFER | I2C_IRQ_ERROR);
/* Configure the slave unit */
if (flags & I2C_SLAVE_DUAL_ADDRESS) {
i2c_slave_dual_address_enable(dev);
}
if (flags & I2C_SLAVE_GENERAL_CALL) {
i2c_slave_general_call_enable(dev);
}
/* store all of the flags */
dev->config_flags = flags;
/* Make it go! */
i2c_peripheral_enable(dev);
i2c_enable_ack(dev);
dev->state = I2C_STATE_IDLE;
}
/* (Called from exc.S with global interrupts disabled.) */
void __error(void) {
/* Turn off peripheral interrupts */
nvic_irq_disable_all();
/* Turn off timers */
timer_disable_all();
/* Turn off ADC */
adc_disable_all();
/* Turn off all USARTs */
usart_disable_all();
/* Turn the USB interrupt back on so the bootloader keeps on functioning */
nvic_irq_enable(NVIC_USB_HP_CAN_TX);
nvic_irq_enable(NVIC_USB_LP_CAN_RX0);
/* Reenable global interrupts */
nvic_globalirq_enable();
throb();
}
void SPI1_IRQHandler(void) {
static rt_uint8_t is_cmd;
static rt_uint8_t cmd;
rt_interrupt_enter();
if(spi_is_rx_nonempty(spi1.c_dev())) {
nvic_irq_disable(NVIC_SPI1);
if(!is_cmd) {
cmd = spi1.read();
}
is_cmd = !is_cmd;
wrtnode2r_spi_bridge_rx_isr(cmd, is_cmd);
nvic_irq_enable(NVIC_SPI1);
}
rt_interrupt_leave();
}
/* Basic and general purpose timers have a single IRQ line, which is
* shared by all interrupts supported by a particular timer. */
static void enable_bas_gen_irq(timer_dev *dev) {
nvic_irq_num irq_num;
switch (dev->clk_id) {
case RCC_TIMER2:
irq_num = NVIC_TIMER2;
break;
case RCC_TIMER3:
irq_num = NVIC_TIMER3;
break;
case RCC_TIMER4:
irq_num = NVIC_TIMER4;
break;
case RCC_TIMER5:
irq_num = NVIC_TIMER5;
break;
case RCC_TIMER6:
irq_num = NVIC_TIMER6;
break;
case RCC_TIMER7:
irq_num = NVIC_TIMER7;
break;
case RCC_TIMER9:
irq_num = NVIC_TIMER1_BRK_TIMER9;
break;
case RCC_TIMER10:
irq_num = NVIC_TIMER1_UP_TIMER10;
break;
case RCC_TIMER11:
irq_num = NVIC_TIMER1_TRG_COM_TIMER11;
break;
case RCC_TIMER12:
irq_num = NVIC_TIMER8_BRK_TIMER12;
break;
case RCC_TIMER13:
irq_num = NVIC_TIMER8_UP_TIMER13;
break;
case RCC_TIMER14:
irq_num = NVIC_TIMER8_TRG_COM_TIMER14;
break;
default:
ASSERT_FAULT(0);
return;
}
nvic_irq_enable(irq_num);
}
/* NOTE: Nothing specific to this device class in this function, but depenedent on the device, move to usb_lib or stm32fxx*/
static void usbInit(void) {
pInformation->Current_Configuration = 0;
USB_BASE->CNTR = USB_CNTR_FRES;
USBLIB->irq_mask = 0;
USB_BASE->CNTR = USBLIB->irq_mask;
USB_BASE->ISTR = 0;
USBLIB->irq_mask = USB_CNTR_RESETM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
USB_BASE->CNTR = USBLIB->irq_mask;
USB_BASE->ISTR = 0;
USBLIB->irq_mask = USB_ISR_MSK;
USB_BASE->CNTR = USBLIB->irq_mask;
nvic_irq_enable(NVIC_USB_LP_CAN_RX0);
USBLIB->state = USB_UNCONNECTED;
}
/*!
\brief main function
\param[in] none
\param[out] none
\retval none
*/
int main(void)
{
/* NVIC config */
nvic_priority_group_set(NVIC_PRIGROUP_PRE0_SUB4);
nvic_irq_enable(LVD_IRQn,0,0);
/* clock enable */
rcu_periph_clock_enable(RCU_PMU);
/* led1 config */
gd_eval_ledinit (LED1);
/* led1 turn on */
gd_eval_ledon(LED1);
/* EXTI_16 config */
exti_init(EXTI_16, EXTI_INTERRUPT, EXTI_TRIG_BOTH);
/* configure the lvd threshold to 2.9v(gd32f130_150) or 4.5v(gd32f170_190), and enable the lvd */
pmu_lvd_select(PMU_LVDT_7);
while(1);
}
/*!
\brief configure TIMER
\param[in] none
\param[out] none
\retval none
*/
void timer_config(void)
{
/* initialize TIMER1 */
timer_parameter_struct timer_init_parameter;
timer_init_parameter.timer_prescaler = 0;
timer_init_parameter.timer_counterdirection = TIMER_COUNTER_UP;
timer_init_parameter.timer_period = 65535;
timer_init_parameter.timer_clockrivision = TIMER_CKDIV_DIV1;
timer_init(TIMER1, &timer_init_parameter);
/* clear flag */
timer_flag_clear(TIMER1, TIMER_FLAG_UPIF);
nvic_irq_enable(TIMER1_IRQn, 0, 0);
/* reset TIMER1 interrupt flag register */
TIMER_INTF(TIMER1) = 0;
timer_interrupt_enable(TIMER1, TIMER_INT_CH3IE);
/* enable TIMER1 counter */
timer_enable(TIMER1);
}
void dma_attach_interrupt(dma_dev *dev, dma_channel channel,
void (*handler)(void)) {
DMA_GET_HANDLER(dev, channel) = handler;
nvic_irq_enable(dev->handlers[channel - 1].irq_line);
}
/**
* @brief Attach an interrupt to a DMA transfer.
*
* Interrupts are enabled using appropriate mode flags in
* dma_setup_transfer().
*
* @param dev DMA device
* @param channel Channel to attach handler to
* @param handler Interrupt handler to call when channel interrupt fires.
* @see dma_setup_transfer()
* @see dma_get_irq_cause()
* @see dma_detach_interrupt()
*/
void dma_attach_interrupt(dma_dev *dev,
dma_channel channel,
void (*handler)(void)) {
dev->handlers[channel - 1].handler = handler;
nvic_irq_enable(dev->handlers[channel - 1].irq_line);
}
/*
enable interrupts on the ADC:
use ADC_EOC, ADC_JEOC, ADC_AWD
This will set up the interrupt bit in the ADC as well as in the NVIC.
added by bubulindo
*/
void adc_enable_irq(adc_dev* dev, uint8 interrupt) {//ADC1 for now.
dev->regs->CR1 |= (1U<<(interrupt +ADC_CR1_EOCIE_BIT));
nvic_irq_enable(dev->irq_num);
}
rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
const struct pin_index *index;
const struct pin_irq_map *irqmap;
rt_base_t level;
rt_int32_t hdr_index = -1;
exti_trig_type_enum trigger_mode;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
}
if (enabled == PIN_IRQ_ENABLE)
{
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[hdr_index].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EINVAL;
}
irqmap = &pin_irq_map[hdr_index];
switch (pin_irq_hdr_tab[hdr_index].mode)
{
case PIN_IRQ_MODE_RISING:
trigger_mode = EXTI_TRIG_RISING;
break;
case PIN_IRQ_MODE_FALLING:
trigger_mode = EXTI_TRIG_FALLING;
break;
case PIN_IRQ_MODE_RISING_FALLING:
trigger_mode = EXTI_TRIG_BOTH;
break;
default:
rt_hw_interrupt_enable(level);
return RT_EINVAL;
}
//rcu_periph_clock_enable(RCU_AF);
/* enable and set interrupt priority */
nvic_irq_enable(irqmap->irqno, 5U);
/* connect EXTI line to GPIO pin */
syscfg_exti_line_config(index->port_src, index->pin_src);
/* configure EXTI line */
exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
exti_interrupt_flag_clear((exti_line_enum)(index->pin));
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
irqmap = get_pin_irq_map(index->pin);
if (irqmap == RT_NULL)
{
return RT_EINVAL;
}
nvic_irq_disable(irqmap->irqno);
}
else
{
return RT_EINVAL;
}
return RT_EOK;
}
/*
Enable the Analog Watchdog interrupt
*/
void enable_awd_irq(adc_dev * dev){
dev->regs->CR1 |= (1U<<ADC_CR1_AWDIE_BIT);
nvic_irq_enable(NVIC_ADC_1_2 );
}
/*
Enable end of conversion interrupt on the ADC.
This is for regular conversion, not injected.
*/
void enable_adc_irq(adc_dev* dev) {//ADC1 for now.
dev->regs->CR1 |= (1U<<ADC_CR1_EOCIE_BIT);
nvic_irq_enable(NVIC_ADC_1_2 );
}
/**
* @brief Attach an interrupt to a DMA transfer.
*
* Interrupts are enabled using appropriate mode flags in
* dma_setup_transfer().
*
* @param dev DMA device
* @param stream Stream to attach handler to
* @param handler Interrupt handler to call when channel interrupt fires.
* @see dma_setup_transfer()
* @see dma_detach_interrupt()
*/
void dma_attach_interrupt(dma_dev *dev,
dma_stream stream,
void (*handler)(void)) {
dev->handlers[stream].handler = handler;
nvic_irq_enable(dev->handlers[stream].irq_line);
}
/**
* @brief Initialize an I2C device as bus master
* @param dev Device to enable
* @param flags Bitwise or of the following I2C options:
* I2C_FAST_MODE: 400 khz operation,
* I2C_DUTY_16_9: 16/9 Tlow/Thigh duty cycle (only applicable for
* fast mode),
* I2C_BUS_RESET: Reset the bus and clock out any hung slaves on
* initialization,
* I2C_10BIT_ADDRESSING: Enable 10-bit addressing,
* I2C_REMAP: Remap I2C1 to SCL/PB8 SDA/PB9.
*/
void i2c_master_enable(i2c_dev *dev, uint32 flags) {
#define I2C_CLK (STM32_PCLK1/1000000)
uint32 ccr = 0;
uint32 trise = 0;
/* PE must be disabled to configure the device */
ASSERT(!(dev->regs->CR1 & I2C_CR1_PE));
if ((dev == I2C1) && (flags & I2C_REMAP)) {
afio_remap(AFIO_REMAP_I2C1);
I2C1->sda_pin = 9;
I2C1->scl_pin = 8;
}
/* Reset the bus. Clock out any hung slaves. */
if (flags & I2C_BUS_RESET) {
i2c_bus_reset(dev);
}
/* Turn on clock and set GPIO modes */
i2c_init(dev);
gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_AF_OUTPUT_OD);
gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_AF_OUTPUT_OD);
/* I2C1 and I2C2 are fed from APB1, clocked at 36MHz */
i2c_set_input_clk(dev, I2C_CLK);
if (flags & I2C_FAST_MODE) {
ccr |= I2C_CCR_FS;
if (flags & I2C_DUTY_16_9) {
/* Tlow/Thigh = 16/9 */
ccr |= I2C_CCR_DUTY;
ccr |= STM32_PCLK1/(400000 * 25);
} else {
/* Tlow/Thigh = 2 */
ccr |= STM32_PCLK1/(400000 * 3);
}
trise = (300 * (I2C_CLK)/1000) + 1;
} else {
/* Tlow/Thigh = 1 */
ccr = STM32_PCLK1/(100000 * 2);
trise = I2C_CLK + 1;
}
/* Set minimum required value if CCR < 1*/
if ((ccr & I2C_CCR_CCR) == 0) {
ccr |= 0x1;
}
i2c_set_clk_control(dev, ccr);
i2c_set_trise(dev, trise);
/* Enable event and buffer interrupts */
nvic_irq_enable(dev->ev_nvic_line);
nvic_irq_enable(dev->er_nvic_line);
i2c_enable_irq(dev, I2C_IRQ_EVENT | I2C_IRQ_BUFFER | I2C_IRQ_ERROR);
/*
* Important STM32 Errata:
*
* See STM32F10xx8 and STM32F10xxB Errata sheet (Doc ID 14574 Rev 8),
* Section 2.11.1, 2.11.2.
*
* 2.11.1:
* When the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8, and EV3 events are not
* managed before the current byte is being transferred, problems may be
* encountered such as receiving an extra byte, reading the same data twice
* or missing data.
*
* 2.11.2:
* In Master Receiver mode, when closing the communication using
* method 2, the content of the last read data can be corrupted.
*
* If the user software is not able to read the data N-1 before the STOP
* condition is generated on the bus, the content of the shift register
* (data N) will be corrupted. (data N is shifted 1-bit to the left).
*
* ----------------------------------------------------------------------
*
* In order to ensure that events are not missed, the i2c interrupt must
* not be preempted. We set the i2c interrupt priority to be the highest
* interrupt in the system (priority level 0). All other interrupts have
* been initialized to priority level 16. See nvic_init().
*/
nvic_irq_set_priority(dev->ev_nvic_line, 0);
nvic_irq_set_priority(dev->er_nvic_line, 0);
/* Make it go! */
i2c_peripheral_enable(dev);
dev->state = I2C_STATE_IDLE;
}
