/*************************************************************************
* DESCRIPTION: Copy the name from non-volatile memory at offset
* RETURN: number of bytes read, or -1 on error
* NOTES: none
**************************************************************************/
int bacnet_name_copy(
uint16_t offset,
uint8_t *dest,
uint8_t dest_len)
{
uint8_t encoding = 0;
uint8_t length = 0;
char name[NVM_NAME_SIZE + 1] = "";
unsigned i = 0;
int bytes_read = -1;
nvm_read(NVM_NAME_ENCODING(offset), &encoding, 1);
nvm_read(NVM_NAME_LENGTH(offset), &length, 1);
nvm_read(NVM_NAME_STRING(offset),
(uint8_t *) & name, NVM_NAME_SIZE);
if (bacnet_name_isvalid(encoding, length, name)) {
if (dest_len > NVM_NAME_SIZE) {
dest_len = NVM_NAME_SIZE;
}
bytes_read = dest_len;
for (i = 0; i < dest_len; i++) {
if (i < length) {
dest[i] = name[i];
} else {
dest[i] = 0;
}
}
} else {
for (i = 0; i < dest_len; i++) {
dest[i] = 0;
}
}
return bytes_read;
}
/* load the config from flash to the pass conf structure */
void mc1322x_config_restore(mc1322xConfig *c) {
nvmErr_t err;
nvmType_t type;
if (c->flags.nvmtype == 0) { nvm_detect(gNvmInternalInterface_c, &type); }
c->flags.nvmtype = type;
err = nvm_read(gNvmInternalInterface_c, c->flags.nvmtype, c, MC1322X_CONFIG_PAGE, sizeof(mc1322xConfig));
}
/*! \brief Test routine that writes to the non volatile memory, reads back
* and compares the values
*/
static status_code_t test_mem(mem_type_t mem, uint32_t test_address)
{
static uint8_t write_buf[8]
= {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF};
static uint8_t read_buf[8], i = 0;
/* Initialize the non volatile memory */
if (nvm_init(mem) != STATUS_OK) {
return ERR_INVALID_ARG;
}
/* Write test pattern to the specified address */
nvm_write(mem, test_address, (void *)write_buf, sizeof(write_buf));
/* Read back data from the same address */
nvm_read(mem, test_address, (void *)read_buf, sizeof(read_buf));
/* Validate the read data */
for (i = 0; i < sizeof(write_buf); i++) {
if (read_buf[i] != write_buf[i]) {
return ERR_BAD_DATA;
}
}
return STATUS_OK;
}
void bacnet_name(uint16_t offset,
BACNET_CHARACTER_STRING * char_string,
char *default_string)
{
uint8_t encoding = 0;
uint8_t length = 0;
char name[NVM_NAME_SIZE + 1] = "";
nvm_read(NVM_NAME_ENCODING(offset), &encoding, 1);
nvm_read(NVM_NAME_LENGTH(offset), &length, 1);
nvm_read(NVM_NAME_STRING(offset), (uint8_t *) & name[0], NVM_NAME_SIZE);
if (bacnet_name_isvalid(encoding, length, name)) {
characterstring_init(char_string, encoding, &name[0], length);
} else if (default_string) {
characterstring_init_ansi(char_string, default_string);
}
}
retval_t pal_ps_get(ps_type_t mem_type, uint16_t offset, uint16_t length,
void *value)
{
nvm_read(INT_FLASH,
(uint32_t)offset + INT_FLASH_END - STACK_FLASH_SIZE + 1,
value,
length);
return MAC_SUCCESS;
}
void main(void) {
nvmType_t type=0;
nvmErr_t err;
uint32_t buf[WRITE_NBYTES/4];
uint32_t i;
uart_init(INC, MOD, SAMP);
print_welcome("nvm-write");
vreg_init();
if(NVM_INTERFACE == gNvmInternalInterface_c)
{
printf("Detecting internal nvm\n\r");
} else {
printf("Setting up gpio\r\n");
/* set SPI func */
GPIO->FUNC_SEL.GPIO_04 = 1;
GPIO->FUNC_SEL.GPIO_05 = 1;
GPIO->FUNC_SEL.GPIO_06 = 1;
GPIO->FUNC_SEL.GPIO_07 = 1;
printf("Detecting external nvm\n\r");
}
err = nvm_detect(NVM_INTERFACE, &type);
printf("nvm_detect returned: 0x%02x type is: 0x%08x\r\n", err, (unsigned int)type);
buf[0] = WRITEVAL0;
buf[1] = WRITEVAL1;
err = nvm_erase(NVM_INTERFACE, type, 1 << WRITE_ADDR/4096);
printf("nvm_erase returned: 0x%02x\r\n", err);
err = nvm_write(NVM_INTERFACE, type, (uint8_t *)buf, WRITE_ADDR, WRITE_NBYTES);
printf("gnychis nvm_write returned: 0x%02x\r\n", err);
printf("writing\n\r");
for(i=0; i<WRITE_NBYTES/4; i++) {
printf("0x%08x\r\n", (unsigned int)buf[i]);
buf[i] = 0x00000000; /* clear buf for the read */
}
err = nvm_read(NVM_INTERFACE, type, (uint8_t *)buf, WRITE_ADDR, WRITE_NBYTES);
printf("nvm_read returned: 0x%02x\r\n", err);
printf("reading\r\n");
for(i=0; i<WRITE_NBYTES/4; i++) {
printf("0x%08x\r\n", (unsigned int)buf[i]);
}
while(1) {continue;};
}
void dump_bytes(uint32_t addr, uint16_t num) {
uint32_t buf[num/4];
nvmErr_t err;
uint16_t i;
err = nvm_read(gNvmInternalInterface_c, mc1322x_config.flags.nvmtype, (uint8_t *)buf, addr, num);
PRINTF("nvm_read returned: 0x%02x\r\n", err);
for(i=0; i < num/4; i++) {
printf("0x%08x\r\n", (unsigned int)buf[i]);
}
}
void
nvm_data_read(void)
{
nvmType_t type = 0;
nvmErr_t err;
LOG6LBR_INFO("Reading 6LBR NVM\n");
err = nvm_detect(gNvmInternalInterface_c, &type);
err =
nvm_read(gNvmInternalInterface_c, type, (uint8_t *) & nvm_data,
CETIC_6LBR_NVM_ADDRESS, sizeof(nvm_data_t));
if (err) {
LOG6LBR_ERROR("read error : %d\n", err);
}
}
/**
* \brief Test the read and write buffer operations on the NVM
*
* This function will test the read and write functionalities of the NVM
* using buffer access. It will first fill a buffer with a known pattern and
* read it back by testing each value read.\n
*
* \param test Current test case.
*/
static void run_buffer_access_test(const struct test_case *test)
{
status_code_t status;
uint8_t i, test_buf[20];
/* Fills a test buffer with a known pattern
*/
for (i = 0; i < 20; i++) {
test_buf[i] = BYTE_PATTERN2(i);
}
/* Write the buffer to the non volatile memory */
status = nvm_write(INT_FLASH, (uint32_t)TEST_ADDRESS, (void *)test_buf,
sizeof(test_buf));
test_assert_true(test, status == STATUS_OK,
"Write buffer operation error");
/* Clear the test buffer */
for (i = 0; i < 20; i++) {
test_buf[i] = 0;
}
/* Read back the non volatile memory */
status = nvm_read(INT_FLASH, (uint32_t)TEST_ADDRESS, (void *)test_buf,
sizeof(test_buf));
test_assert_true(test, status == STATUS_OK,
"Read buffer operation error");
/* Compare the values read from the NVM with the expected values
*/
for (i = 0; i < 20; i++) {
test_assert_true(test, test_buf[i] == BYTE_PATTERN2(i),
"Value not expected @ byte %d (read: 0x%02x,"
" expected: 0x%02x)", i, test_buf[i],
BYTE_PATTERN2(i));
}
}
int main(void) {
nvmType_t type=0;
nvmErr_t err;
volatile uint8_t c;
volatile uint32_t i;
volatile uint32_t buf[4];
volatile uint32_t len=0;
volatile uint32_t state = SCAN_X;
volatile uint32_t addr,data;
uart_init(UART1, 115200);
disable_irq(UART1);
vreg_init();
dbg_putstr("Detecting internal nvm\n\r");
err = nvm_detect(gNvmInternalInterface_c, &type);
dbg_putstr("nvm_detect returned: 0x");
dbg_put_hex(err);
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)nvm_base, NVM_BASE, 0x100);
dbg_putstr("nvm_read returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
/* erase the flash */
nvm_setsvar(0);
err = nvm_erase(gNvmInternalInterface_c, type, 0x40000000);
dbg_putstr("nvm_erase returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)nvm_base, NVM_BASE, 0x100);
dbg_putstr("nvm_write returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
/* say we are ready */
len = 0;
putstr("ready");
flushrx();
/* read the length */
for(i=0; i<4; i++) {
c = uart1_getc();
/* bail if the first byte of the length is zero */
len += (c<<(i*8));
}
dbg_putstr("len: ");
dbg_put_hex32(len);
dbg_putstr("\n\r");
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
putstr("flasher done\n\r");
state = SCAN_X; addr=0;
while((c=getc())) {
if(state == SCAN_X) {
/* read until we see an 'x' */
if(c==0) { break; }
if(c!='x'){ continue; }
/* go to read_chars once we have an 'x' */
state = READ_CHARS;
i = 0;
}
if(state == READ_CHARS) {
/* read all the chars up to a ',' */
((uint8_t *)buf)[i++] = c;
/* after reading a ',' */
/* goto PROCESS state */
if((c == ',') || (c == 0)) { state = PROCESS; }
}
if(state == PROCESS) {
if(addr==0) {
/*interpret the string as the starting address */
addr = to_u32(buf);
} else {
/* string is data to write */
data = to_u32(buf);
putstr("writing addr ");
put_hex32(NVM_BASE+addr);
putstr(" data ");
put_hex32(data);
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&data, NVM_BASE+addr, 4);
addr += 4;
putstr(" err ");
put_hex32(err);
putstr("\n\r");
}
/* look for the next 'x' */
state=SCAN_X;
}
}
putstr("process flasher done\n\r");
while(1) {continue;};
}
void _AJ_NV_Read(void* src, void* buf, uint16_t size)
{
nvm_read(INT_FLASH, (uint32_t)src, buf, size);
}
void main(void) {
nvmType_t type=0;
nvmErr_t err;
volatile uint8_t c;
volatile uint32_t i;
volatile uint32_t buf[4];
volatile uint32_t len=0;
volatile uint32_t state = SCAN_X;
volatile uint32_t addr,data;
uart_init(UART1, 115200);
disable_irq(UART1);
vreg_init();
dbg_putstr("Detecting internal nvm\n\r");
err = nvm_detect(gNvmInternalInterface_c, &type);
dbg_putstr("nvm_detect returned: 0x");
dbg_put_hex(err);
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
/* erase the flash */
err = nvm_erase(gNvmInternalInterface_c, type, 0x7fffffff);
dbg_putstr("nvm_erase returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
/* say we are ready */
len = 0;
putstr("ready");
flushrx();
/* read the length */
for(i=0; i<4; i++) {
c = uart1_getc();
/* bail if the first byte of the length is zero */
len += (c<<(i*8));
}
dbg_putstr("write_len: 0x");
dbg_put_hex32(len);
dbg_putstr("\n\r");
/* write the OKOK magic */
#if BOOT_OK
((uint8_t *)buf)[0] = 'O'; ((uint8_t *)buf)[1] = 'K'; ((uint8_t *)buf)[2] = 'O'; ((uint8_t *)buf)[3] = 'K';
#elif BOOT_SECURE
((uint8_t *)buf)[0] = 'S'; ((uint8_t *)buf)[1] = 'E'; ((uint8_t *)buf)[2] = 'C'; ((uint8_t *)buf)[3] = 'U';
#else
((uint8_t *)buf)[0] = 'N'; ((uint8_t *)buf)[1] = 'O'; ((uint8_t *)buf)[2] = 'N'; ((uint8_t *)buf)[3] = 'O';
#endif
/* don't make a valid boot image if the received length is zero */
if(len == 0) {
((uint8_t *)buf)[0] = 'N';
((uint8_t *)buf)[1] = 'O';
((uint8_t *)buf)[2] = 'N';
((uint8_t *)buf)[3] = 'O';
}
uint32_t err_count = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)buf, 0, 4);
/* read a byte, write a byte, including the first 4 len bytes */
for(i=0; i<len; i++) {
c = getc();
err_count += nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&c, 4+i, 1);
}
if (err_count > 0) {
dbg_putstr("ALERT nvm_write error-count: ");
dbg_put_hex32(err_count);
dbg_putstr("\n\r");
} else {
dbg_putstr("write successfully done\n\r");
}
/* read and output real len */
err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *) &len, 4, 4);
dbg_putstr("prog_len: 0x");
dbg_put_hex32(len);
dbg_putstr("\n\r");
putstr("flasher done\n\r");
state = SCAN_X; addr=0;
while((c=getc())) {
if(state == SCAN_X) {
/* read until we see an 'x' */
if(c==0) { break; }
if(c!='x'){ continue; }
/* go to read_chars once we have an 'x' */
state = READ_CHARS;
i = 0;
}
if(state == READ_CHARS) {
/* read all the chars up to a ',' */
((uint8_t *)buf)[i++] = c;
/* after reading a ',' */
/* goto PROCESS state */
if((c == ',') || (c == 0)) { state = PROCESS; }
}
if(state == PROCESS) {
if(addr==0) {
/*interpret the string as the starting address */
addr = to_u32(buf);
} else {
/* string is data to write */
data = to_u32(buf);
putstr("writing addr ");
put_hex32(addr);
putstr(" data ");
put_hex32(data);
putstr("\n\r");
err = nvm_write(gNvmInternalInterface_c, 1, (uint8_t *)&data, addr, 4);
addr += 4;
}
/* look for the next 'x' */
state=SCAN_X;
}
}
while(1) {continue;};
}
