Example #1
0
void lltime_start(void)
{
	int ch = CFG_TIMER_DBG_TICK_CH;
	ulong count = (-1UL), val;
	int mux = __timer_sys_mux_val;
	int scl = __timer_sys_scl_val;

	if (true == __dbg_timer_run)
		return;

	if (!nxp_soc_peri_reset_status(RESET_ID_TIMER))
		nxp_soc_peri_reset_set(RESET_ID_TIMER);

	/* clock gen : enable */
	if (5 == mux) {
		uint clr = __timer_sys_clk_clr;
		uint enb = readl(TIMER_SYS_CLKGEN + CLKGEN_ENB);
		writel(clr , TIMER_DBG_CLKGEN + CLKGEN_CLR);
		writel((enb | 1<<2), TIMER_DBG_CLKGEN + CLKGEN_ENB);
	}

	/* Timer : stop */
	val  = readl(TIMER_BASE + TIMER_TCON);
	val &= ~(TCON_RUN << TCON_CH(ch));
	writel(val, TIMER_BASE + TIMER_TCON);

	/* Timer : prescaler (clock) */
	val = readl(TIMER_BASE + TIMER_CFG0);
	val &= ~(0xFF   << CFG0_CH(ch));
	val |=  ((scl-1)<< CFG0_CH(ch));
	writel(val, (TIMER_BASE + TIMER_CFG0));

	/* Timer : mux (clock) */
	val = readl(TIMER_BASE + TIMER_CFG1);
	val &= ~(0xF << CFG1_CH(ch));
	val |=  (mux << CFG1_CH(ch));
	writel(val, (TIMER_BASE + TIMER_CFG1));

	/* Timer : count */
	writel(count, TIMER_BASE + TIMER_CNTB + (TIMER_CH_OFFS * ch));
	writel(count, TIMER_BASE + TIMER_CMPB + (TIMER_CH_OFFS * ch));

	/* Timer : start */
	val  = readl(TIMER_BASE + TIMER_STAT);
	val &= ~(TINT_CS_MASK<<5 | 0x1 << TINT_CH(ch));
	val |=  (0x1 << TINT_CS_CH(ch) | 0 << TINT_CH(ch));
	writel(val, TIMER_BASE + TIMER_STAT);

	val = readl(TIMER_BASE + TIMER_TCON);
	val &= ~(0xE << TCON_CH(ch));
	val |=  (TCON_UP << TCON_CH(ch));
	writel(val, TIMER_BASE + TIMER_TCON);

	val &= ~(TCON_UP << TCON_CH(ch));
	val |=  ((TCON_AUTO | TCON_RUN)  << TCON_CH(ch));
	writel(val, TIMER_BASE + TIMER_TCON);

	__dbg_timer_run = true;
}
Example #2
0
static int __dwmci_initialize(int ch, ulong rate)
{
	struct clk *clk = NULL;
	int reset = RESET_ID_SDMMC0 + ch;
	char s[20];

	nxp_soc_peri_reset_set(reset);

	sprintf(s, "%s.%d", DEV_NAME_SDHC, ch);
	clk = clk_get(NULL, s);
	clk_set_rate(clk, rate);
	clk_enable(clk);
	return 0;
}
Example #3
0
inline static void uart_init(void)
{
	U32 CLKENB = UART_CLKG_BASE;
	U32 CLKGEN = UART_CLKG_BASE + 0x04;
	struct uart_data *pdat = &udata;
	struct s5p_uart *uart = (struct s5p_uart *)UART_PHYS_BASE;
	unsigned int baudrate = UART_DEBUG_BAUDRATE;
	unsigned int clkval;

	/* Clock Generotor & reset */
	if (0 == pdat->rate) {
		u32 val = UART_DEBUG_HZ / baudrate;
		pdat->rate = calc_uart_clock(UART_DEBUG_HZ, &pdat->pll, &pdat->div);
		pdat->ubrdiv = (val/16) - 1;
		pdat->udivslot = udivslot[val % 16];
		/* NORMAL | No parity | 1 stop | 8bit */
		pdat->ulcon = (((0 & 0x1)<<6) | ((0 & 0x3)<<3) | ((0 & 0x1)<<2) | ((3 & 0x3)<<0));
		/* Tx FIFO clr | Rx FIFO clr | FIFOs EN */
		pdat->ufcon = (((1 & 0x1)<<1) | ((1 & 0x1)<<0));
	}

	/* check reset */
	if (!nxp_soc_peri_reset_status(RESET_UART_ID)) {
		NX_TIEOFF_Set(TIEOFF_USESMC  , 0);
		NX_TIEOFF_Set(TIEOFF_SMCTXENB, 0);
		NX_TIEOFF_Set(TIEOFF_SMCRXENB, 0);
		nxp_soc_peri_reset_set(RESET_UART_ID);
	}

	/* check pll : alaway enable clkgen */
	clkval = readl(CLKGEN) & ~(0x07<<2) & ~(0xFF<<5);
	writel((clkval|(pdat->pll<<2)|((pdat->div-1)<<5)), CLKGEN);
	writel((readl(CLKENB)|(1<<2)), CLKENB);

	/* Uart Register */
	writel(pdat->ufcon, &uart->ufcon);
	writel(pdat->ulcon, &uart->ulcon);
	writel(pdat->ubrdiv, &uart->ubrdiv);
	writew(pdat->udivslot, &uart->rest.slot);
}
Example #4
0
static void inline spdif_reset(struct nxp_spdif_snd_param *par)
{
	nxp_soc_peri_reset_set(RESET_ID_SPDIFRX);
}
Example #5
0
static int __devinit nxp_wdt_probe(struct platform_device *pdev)
{
	struct device *dev;
	unsigned int wtcon;
	int started = 0;
	int ret;
	int size;
#ifdef CONFIG_WDT_SYSFS
    struct kobject *kobj = NULL;
#endif

	DBG("%s: probe=%p\n", __func__, pdev);

	dev = &pdev->dev;
	wdt_dev = &pdev->dev;

	wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (wdt_mem == NULL) {
		dev_err(dev, "no memory resource specified\n");
		return -ENOENT;
	}

	wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (wdt_irq == NULL) {
		dev_err(dev, "no irq resource specified\n");
		ret = -ENOENT;
		goto err;
	}

	/* get the memory region for the watchdog timer */

	size = resource_size(wdt_mem);
	if (!request_mem_region(wdt_mem->start, size, pdev->name)) {
		dev_err(dev, "failed to get memory region\n");
		ret = -EBUSY;
		goto err;
	}

	wdt_clock = clk_get(NULL, "pclk");
	if (IS_ERR(wdt_clock)) {
		dev_err(dev, "failed to find watchdog clock source\n");
		ret = PTR_ERR(wdt_clock);
		goto err_map;
	}

	clk_enable(wdt_clock);
	wdt_freq = clk_get_rate(wdt_clock);

	nxp_wdt_bclk_dfs_register();

	nxp_soc_peri_reset_set(RESET_ID_WDT);
	nxp_soc_peri_reset_set(RESET_ID_WDT_POR);

	/* if we're not enabling the watchdog, then ensure it is
	 * disabled if it has been left running from the bootloader
	 * or other source */
	nxp_wdt_stop(&nxp_wdd);

	/* see if we can actually set the requested timer margin, and if
	 * not, try the default value */

	if (nxp_wdt_set_heartbeat(&nxp_wdd, tmr_margin)) {
		started = nxp_wdt_set_heartbeat(&nxp_wdd,
#ifdef CONFIG_WDT_TASK
					CONFIG_DEFAULT_WDT_TASK_TIMEOUT);
#else
					CONFIG_NXP_WATCHDOG_DEFAULT_TIME);
#endif

		if (started == 0)
			dev_info(dev,
			   "tmr_margin value out of range, default %d used\n",
			       CONFIG_NXP_WATCHDOG_DEFAULT_TIME);
		else
			dev_info(dev, "default timer value is out of range, "
							"cannot start\n");
	}
Example #6
0
static void inline pdm_reset(struct nxp_pdm_snd_param *par)
{
	nxp_soc_peri_reset_set(RESET_ID_PDM);
}
Example #7
0
static inline void timer_reset(int ch)
{
	if (!nxp_soc_peri_reset_status(RESET_ID_TIMER))
		nxp_soc_peri_reset_set(RESET_ID_TIMER);
}