static void read_pin_settings(struct device_node *node) { u32 pin; int index; int input_index = 0; for (index = 0; of_property_read_u32_index( node, "brcm,pins", index, &pin) == 0; index++) { u32 function; int err; err = of_property_read_u32_index( node, "brcm,function", index, &function); if (err == 0) { if (function == 1) /* Output */ gpio_out_pin = pin; else if (function == 0) { /* Input */ gpio_in_pin[input_index] = pin; input_index++; } } } }
static int syscon_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct of_device_id *of_id; struct syscon_gpio_priv *priv; struct device_node *np = dev->of_node; int ret; of_id = of_match_device(syscon_gpio_ids, dev); if (!of_id) return -ENODEV; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->data = of_id->data; if (priv->data->compatible) { priv->syscon = syscon_regmap_lookup_by_compatible( priv->data->compatible); if (IS_ERR(priv->syscon)) return PTR_ERR(priv->syscon); } else { priv->syscon = syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev"); if (IS_ERR(priv->syscon)) return PTR_ERR(priv->syscon); ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1, &priv->dreg_offset); if (ret) dev_err(dev, "can't read the data register offset!\n"); priv->dreg_offset <<= 3; ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2, &priv->dir_reg_offset); if (ret) dev_dbg(dev, "can't read the dir register offset!\n"); priv->dir_reg_offset <<= 3; } priv->chip.parent = dev; priv->chip.owner = THIS_MODULE; priv->chip.label = dev_name(dev); priv->chip.base = -1; priv->chip.ngpio = priv->data->bit_count; priv->chip.get = syscon_gpio_get; if (priv->data->flags & GPIO_SYSCON_FEAT_IN) priv->chip.direction_input = syscon_gpio_dir_in; if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) { priv->chip.set = priv->data->set ? : syscon_gpio_set; priv->chip.direction_output = syscon_gpio_dir_out; }
static int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt) { u32 min = 0; u32 max = WDT_COUNTER_MAX_SECS; const char *tmp; /* Get the interrupts property */ wdt->irq = irq_of_parse_and_map(np, 0); if (!wdt->irq) dev_warn(wdt->wdd.parent, "failed to get IRQ from DT\n"); if (!of_property_read_u32_index(np, "atmel,max-heartbeat-sec", 0, &max)) { if (!max || max > WDT_COUNTER_MAX_SECS) max = WDT_COUNTER_MAX_SECS; if (!of_property_read_u32_index(np, "atmel,min-heartbeat-sec", 0, &min)) { if (min >= max) min = max - 1; } } min = secs_to_ticks(min); max = secs_to_ticks(max); wdt->mr_mask = 0x3FFFFFFF; wdt->mr = 0; if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) && !strcmp(tmp, "software")) { wdt->mr |= AT91_WDT_WDFIEN; wdt->mr_mask &= ~AT91_WDT_WDRPROC; } else { wdt->mr |= AT91_WDT_WDRSTEN; } if (!of_property_read_string(np, "atmel,reset-type", &tmp) && !strcmp(tmp, "proc")) wdt->mr |= AT91_WDT_WDRPROC; if (of_property_read_bool(np, "atmel,disable")) { wdt->mr |= AT91_WDT_WDDIS; wdt->mr_mask &= AT91_WDT_WDDIS; } if (of_property_read_bool(np, "atmel,idle-halt")) wdt->mr |= AT91_WDT_WDIDLEHLT; if (of_property_read_bool(np, "atmel,dbg-halt")) wdt->mr |= AT91_WDT_WDDBGHLT; wdt->mr |= max | ((max - min) << 16); return 0; }
static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev) { struct device_node *np = dev->of_node; struct regmap *sys_mgr_base_addr; u32 reg_offset, reg_shift; int ret; struct device_node *np_splitter; struct resource res_splitter; dwmac->interface = of_get_phy_mode(np); sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); if (IS_ERR(sys_mgr_base_addr)) { dev_info(dev, "No sysmgr-syscon node found\n"); return PTR_ERR(sys_mgr_base_addr); } ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); if (ret) { dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n"); return -EINVAL; } ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); if (ret) { dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n"); return -EINVAL; } dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk"); np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0); if (np_splitter) { if (of_address_to_resource(np_splitter, 0, &res_splitter)) { dev_info(dev, "Missing emac splitter address\n"); return -EINVAL; } dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter); if (IS_ERR(dwmac->splitter_base)) { dev_info(dev, "Failed to mapping emac splitter\n"); return PTR_ERR(dwmac->splitter_base); } } dwmac->reg_offset = reg_offset; dwmac->reg_shift = reg_shift; dwmac->sys_mgr_base_addr = sys_mgr_base_addr; dwmac->dev = dev; return 0; }
void mt_usb_otg_init(struct musb *musb) { #ifdef CONFIG_OF usb_node = of_find_compatible_node(NULL, NULL, "mediatek,mt6735-usb20"); if (usb_node == NULL) { pr_err("USB OTG - get USB0 node failed\n"); } else { if (of_property_read_u32_index(usb_node, "iddig_gpio", 0, &iddig_pin)) { iddig_if_config = 0; pr_err("get dtsi iddig_pin fail\n"); } if (of_property_read_u32_index(usb_node, "iddig_gpio", 1, &iddig_pin_mode)) pr_err("get dtsi iddig_pin_mode fail\n"); if (of_property_read_u32_index(usb_node, "drvvbus_gpio", 0, &drvvbus_pin)) { drvvbus_if_config = 0; pr_err("get dtsi drvvbus_pin fail\n"); } if (of_property_read_u32_index(usb_node, "drvvbus_gpio", 1, &drvvbus_pin_mode)) pr_err("get dtsi drvvbus_pin_mode fail\n"); #if defined(CONFIG_MTK_LEGACY) iddig_pin |= 0x80000000; drvvbus_pin |= 0x80000000; #endif } #if !defined(CONFIG_MTK_LEGACY) pinctrl = devm_pinctrl_get(mtk_musb->controller); if (IS_ERR(pinctrl)) { dev_err(mtk_musb->controller, "Cannot find usb pinctrl!\n"); } #endif #endif /*init drrvbus*/ mt_usb_init_drvvbus(); /* init idpin interrupt */ INIT_DELAYED_WORK(&musb->id_pin_work, musb_id_pin_work); otg_int_init(); /* EP table */ musb->fifo_cfg_host = fifo_cfg_host; musb->fifo_cfg_host_size = ARRAY_SIZE(fifo_cfg_host); otg_state.name = "otg_state"; otg_state.index = 0; otg_state.state = 0; if (switch_dev_register(&otg_state)) pr_err("switch_dev_register fail\n"); else pr_debug("switch_dev register success\n"); }
/* * msm_jpegdma_hw_get_prefetch - Get dma prefetch settings from device-tree. * @dma: Pointer to dma device. */ int msm_jpegdma_hw_get_prefetch(struct msm_jpegdma_device *dma) { int i; int ret; unsigned int cnt; const void *property; property = of_get_property(dma->dev->of_node, "qcom,prefetch-regs", &cnt); if (!property || !cnt) { dev_dbg(dma->dev, "Missing prefetch settings\n"); return 0; } cnt /= 4; dma->prefetch_regs = kcalloc(cnt, sizeof(*dma->prefetch_regs), GFP_KERNEL); if (!dma->prefetch_regs) return -ENOMEM; for (i = 0; i < cnt; i++) { ret = of_property_read_u32_index(dma->dev->of_node, "qcom,prefetch-regs", i, &dma->prefetch_regs[i].reg); if (ret < 0) { dev_err(dma->dev, "can not read prefetch reg %d\n", i); goto error; } ret = of_property_read_u32_index(dma->dev->of_node, "qcom,prefetch-settings", i, &dma->prefetch_regs[i].val); if (ret < 0) { dev_err(dma->dev, "can not read prefetch setting %d\n", i); goto error; } dev_dbg(dma->dev, "Prefetch idx %d, reg %x val %x\n", i, dma->prefetch_regs[i].reg, dma->prefetch_regs[i].val); } dma->prefetch_regs_num = cnt; return 0; error: kfree(dma->prefetch_regs); dma->prefetch_regs = NULL; return ret; }
static int arizona_of_get_micd_configs(struct arizona *arizona, const char *prop) { int nconfigs; int i, j; int ret = 0; u32 value; struct arizona_micd_config *micd_configs; nconfigs = arizona_of_get_u32_num_groups(arizona, prop, 3); if (nconfigs < 0) return nconfigs; micd_configs = devm_kzalloc(arizona->dev, nconfigs * sizeof(struct arizona_micd_config), GFP_KERNEL); for (i = 0, j = 0; i < nconfigs; ++i) { ret = of_property_read_u32_index(arizona->dev->of_node, prop, j++, &value); if (ret < 0) goto error; micd_configs[i].src = value; ret = of_property_read_u32_index(arizona->dev->of_node, prop, j++, &value); if (ret < 0) goto error; micd_configs[i].bias = value; ret = of_property_read_u32_index(arizona->dev->of_node, prop, j++, &value); if (ret < 0) goto error; micd_configs[i].gpio = value; } arizona->pdata.micd_configs = micd_configs; arizona->pdata.num_micd_configs = nconfigs; return ret; error: devm_kfree(arizona->dev, micd_configs); dev_err(arizona->dev, "DT property %s is malformed: %d\n", prop, ret); return ret; }
static void I2S0ConfigParse(struct device_node *node) { if (of_property_read_u32_index(node, AUDDRV_I2S0_CLKGPIO, 0, &(Auddrv_I2S_Setting[Auddrv_I2S0_Setting][Auddrv_I2S_Setting_bck].Gpio_Number))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_I2S0_CLKGPIO); } if (of_property_read_u32_index(node, AUDDRV_I2S0_CLKGPIO, 0, &(Auddrv_I2S_Setting[Auddrv_I2S0_Setting][Auddrv_I2S_Setting_bck].Gpio_Mode))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_I2S0_CLKGPIO); } if (of_property_read_u32_index(node, AUDDRV_I2S0_DATGPIO, 0, &(Auddrv_I2S_Setting[Auddrv_I2S0_Setting][Auddrv_I2S_Setting_D00].Gpio_Number))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_I2S0_DATGPIO); } if (of_property_read_u32_index(node, AUDDRV_I2S0_DATGPIO, 1, &(Auddrv_I2S_Setting[Auddrv_I2S0_Setting][Auddrv_I2S_Setting_D00].Gpio_Mode))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_I2S0_DATGPIO); } if (of_property_read_u32_index(node, AUDDRV_I2S0_DATAINGPIO, 0, &(Auddrv_I2S_Setting[Auddrv_I2S0_Setting][Auddrv_I2S_Setting_I00].Gpio_Number))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_I2S0_DATAINGPIO); } if (of_property_read_u32_index(node, AUDDRV_I2S0_DATAINGPIO, 1, &(Auddrv_I2S_Setting[Auddrv_I2S0_Setting][Auddrv_I2S_Setting_I00].Gpio_Mode))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_I2S0_DATAINGPIO); } if (of_property_read_u32_index(node, AUDDRV_I2S0_MCLKGPIO, 0, &(Auddrv_I2S_Setting[Auddrv_I2S0_Setting][Auddrv_I2S_Setting_Mclk].Gpio_Number))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_I2S0_MCLKGPIO); } if (of_property_read_u32_index(node, AUDDRV_I2S0_MCLKGPIO, 1, &(Auddrv_I2S_Setting[Auddrv_I2S0_Setting][Auddrv_I2S_Setting_Mclk].Gpio_Mode))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_I2S0_MCLKGPIO); } if (of_property_read_u32_index(node, AUDDRV_I2S0_WSGPIO, 0, &(Auddrv_I2S_Setting[Auddrv_I2S0_Setting][Auddrv_I2S_Setting_ws].Gpio_Number))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_I2S0_WSGPIO); } if (of_property_read_u32_index(node, AUDDRV_I2S0_WSGPIO, 1, &(Auddrv_I2S_Setting[Auddrv_I2S0_Setting][Auddrv_I2S_Setting_ws].Gpio_Mode))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_I2S0_WSGPIO); } }
static void _btif_set_default_setting(void) { struct device_node *node = NULL; unsigned int irq_info[3] = {0, 0, 0}; unsigned int phy_base; node = of_find_compatible_node(NULL, NULL, "mediatek,BTIF"); if(node){ mtk_btif.p_irq->irq_id = irq_of_parse_and_map(node,0); /*fixme, be compitable arch 64bits*/ mtk_btif.base = (unsigned long)of_iomap(node, 0); BTIF_INFO_FUNC("get btif irq(%d),register base(0x%lx)\n", mtk_btif.p_irq->irq_id,mtk_btif.base); }else{ BTIF_ERR_FUNC("get btif device node fail\n"); } /* get the interrupt line behaviour */ if (of_property_read_u32_array(node, "interrupts", irq_info, ARRAY_SIZE(irq_info))){ BTIF_ERR_FUNC("get interrupt flag from DTS fail\n"); }else{ mtk_btif.p_irq->irq_flags = irq_info[2]; BTIF_INFO_FUNC("get interrupt flag(0x%x)\n",mtk_btif.p_irq->irq_flags); } if (of_property_read_u32_index(node, "reg", 0, &phy_base)){ BTIF_ERR_FUNC("get register phy base from DTS fail\n"); }else{ BTIF_INFO_FUNC("get register phy base(0x%lx)\n",(unsigned long)phy_base); } }
static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, struct device *dev) { struct device_node *np = dev->of_node; int err; /* Get TX/RX clocks */ dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx"); if (IS_ERR(dwmac->clk_tx)) { dev_err(dev, "No tx clock provided...\n"); return PTR_ERR(dwmac->clk_tx); } dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx"); if (IS_ERR(dwmac->clk_rx)) { dev_err(dev, "No rx clock provided...\n"); return PTR_ERR(dwmac->clk_rx); } /* Get mode register */ dwmac->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon"); if (IS_ERR(dwmac->regmap)) return PTR_ERR(dwmac->regmap); err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg); if (err) dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err); return err; }
static int __init ar79_cpu_intc_of_init( struct device_node *node, struct device_node *parent) { int err, i, count; /* Fill the irq_wb_chan table */ count = of_count_phandle_with_args( node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells"); for (i = 0; i < count; i++) { struct of_phandle_args args; u32 irq = i; of_property_read_u32_index( node, "qca,ddr-wb-channel-interrupts", i, &irq); if (irq >= ARRAY_SIZE(irq_wb_chan)) continue; err = of_parse_phandle_with_args( node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells", i, &args); if (err) return err; irq_wb_chan[irq] = args.args[0]; pr_info("IRQ: Set flush channel of IRQ%d to %d\n", irq, args.args[0]); } return mips_cpu_irq_of_init(node, parent); }
static void get_vdd_rstr_freq(struct bcl_context *bcl, struct device_node *ibat_node) { int ret = 0; struct device_node *phandle = NULL; char *key = NULL; key = "qcom,thermal-handle"; phandle = of_parse_phandle(ibat_node, key, 0); if (!phandle) { pr_err("Thermal handle not present\n"); ret = -ENODEV; goto vdd_rstr_exit; } key = "qcom,levels"; ret = of_property_read_u32_index(phandle, key, 0, &bcl->thermal_freq_limit); if (ret) { pr_err("Error reading property %s. ret:%d\n", key, ret); goto vdd_rstr_exit; } vdd_rstr_exit: if (ret) bcl->thermal_freq_limit = BTM_8084_FREQ_MITIG_LIMIT; return; }
static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) { struct device_node *tcsr; struct device_node *np = dev->of_node; struct resource res; u32 offset; int ret; tcsr = of_parse_phandle(np, "qcom,dload-mode", 0); if (!tcsr) return 0; ret = of_address_to_resource(tcsr, 0, &res); of_node_put(tcsr); if (ret) return ret; ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset); if (ret < 0) return ret; *addr = res.start + offset; return 0; }
static int keystone_rproc_of_get_dev_syscon(struct platform_device *pdev, struct keystone_rproc *ksproc) { struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; int ret; if (!of_property_read_bool(np, "ti,syscon-dev")) { dev_err(dev, "ti,syscon-dev property is absent\n"); return -EINVAL; } ksproc->dev_ctrl = syscon_regmap_lookup_by_phandle(np, "ti,syscon-dev"); if (IS_ERR(ksproc->dev_ctrl)) { ret = PTR_ERR(ksproc->dev_ctrl); return ret; } if (of_property_read_u32_index(np, "ti,syscon-dev", 1, &ksproc->boot_offset)) { dev_err(dev, "couldn't read the boot register offset\n"); return -EINVAL; } return 0; }
static int scpi_clk_add(struct device *dev, struct device_node *np, const struct of_device_id *match) { struct clk **clks; int idx, count; struct scpi_clk_data *clk_data; count = of_property_count_strings(np, "clock-output-names"); if (count < 0) { dev_err(dev, "%s: invalid clock output count\n", np->name); return -EINVAL; } clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL); if (!clk_data) return -ENOMEM; clk_data->clk_num = count; clk_data->clk = devm_kcalloc(dev, count, sizeof(*clk_data->clk), GFP_KERNEL); if (!clk_data->clk) return -ENOMEM; clks = devm_kcalloc(dev, count, sizeof(*clks), GFP_KERNEL); if (!clks) return -ENOMEM; for (idx = 0; idx < count; idx++) { struct scpi_clk *sclk; const char *name; u32 val; sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL); if (!sclk) return -ENOMEM; if (of_property_read_string_index(np, "clock-output-names", idx, &name)) { dev_err(dev, "invalid clock name @ %s\n", np->name); return -EINVAL; } if (of_property_read_u32_index(np, "clock-indices", idx, &val)) { dev_err(dev, "invalid clock index @ %s\n", np->name); return -EINVAL; } sclk->id = val; clks[idx] = scpi_clk_ops_init(dev, match, sclk, name); if (IS_ERR_OR_NULL(clks[idx])) dev_err(dev, "failed to register clock '%s'\n", name); else dev_dbg(dev, "Registered clock '%s'\n", name); clk_data->clk[idx] = sclk; } return of_clk_add_provider(np, scpi_of_clk_src_get, clk_data); }
/*********************************************************** Function: wdg_dbg_disable_all Description: Disable watch dog of A core,C core or M core Input:none return: none History: 1. 20140121 Creat 2. 20140919 modify ************************************************************/ void wdg_dbg_disable_all(void) { struct device_node* np; unsigned int board_id = 0; int ret = 0; np = of_find_compatible_node(NULL, NULL, "arm,sp805"); if (IS_ERR(np)) { printk("Can not find sp805 node\n"); } ret = of_property_read_u32_index(np, "board_id", 0, &board_id); if (ret) { wdg_dbg_disable(DBG_WDG_ACORE); wdg_dbg_disable(DBG_WDG_LOCAL_MCU); } else if(BOARD_ID_INFO == board_id) { wdg_dbg_disable(DBG_WDG_ACORE); wdg_dbg_disable(DBG_WDG_CCORE); wdg_dbg_disable(DBG_WDG_LOCAL_MCU); wdg_dbg_disable(DBG_WDG_GLOBAL_MCU); } }
static int adsp_init_mmio(struct qcom_adsp *adsp, struct platform_device *pdev) { struct device_node *syscon; struct resource *res; int ret; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); adsp->qdsp6ss_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); if (!adsp->qdsp6ss_base) { dev_err(adsp->dev, "failed to map QDSP6SS registers\n"); return -ENOMEM; } syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0); if (!syscon) { dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); return -EINVAL; } adsp->halt_map = syscon_node_to_regmap(syscon); of_node_put(syscon); if (IS_ERR(adsp->halt_map)) return PTR_ERR(adsp->halt_map); ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs", 1, &adsp->halt_lpass); if (ret < 0) { dev_err(&pdev->dev, "no offset in syscon\n"); return ret; } return 0; }
static int __init setup_hifcpubiuctrl_regs(struct device_node *np) { int rc = 0; char *name; struct device_node *syscon_np = NULL; name = "syscon-cpu"; syscon_np = of_parse_phandle(np, name, 0); if (!syscon_np) { pr_err("can't find phandle %s\n", name); rc = -EINVAL; goto cleanup; } cpubiuctrl_block = of_iomap(syscon_np, 0); if (!cpubiuctrl_block) { pr_err("iomap failed for cpubiuctrl_block\n"); rc = -EINVAL; goto cleanup; } rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG, &cpu0_pwr_zone_ctrl_reg); if (rc) { pr_err("failed to read 1st entry from %s property (%d)\n", name, rc); rc = -EINVAL; goto cleanup; } rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG, &cpu_rst_cfg_reg); if (rc) { pr_err("failed to read 2nd entry from %s property (%d)\n", name, rc); rc = -EINVAL; goto cleanup; } cleanup: if (syscon_np) of_node_put(syscon_np); return rc; }
static void hwadp_dts_register_base_addr(void) { struct device_node *node = NULL, *np = NULL; int retval = 0; const char * nmi_node = "hisilicon,mdrv_nmi_interrupt_regs"; unsigned int nmi_regs_val[NMI_INT_CORE_NUM] = {0,}; node = of_find_compatible_node(NULL, NULL, "hisilicon,hardware_adapt"); if (!node) { hwadp_printf("dts node not found!\n"); return; } for_each_available_child_of_node(node, np) { unsigned int ip_type = ~0U, int_type = ~0U, irq_num = ~0U; int na = 0, ns = 0, len = 0; unsigned long base_addr = 0; const __be32 *prop = NULL; if(!np->name || !strlen(np->name)) continue; /* try to obtain ip base address */ na = of_n_addr_cells(np); ns = of_n_size_cells(np); prop = of_get_property(np, "reg", &len); retval = of_property_read_u32(np, "ip_type", &ip_type); if(prop && (len == (na + ns) * (int)sizeof(*prop))) { base_addr = (unsigned long)of_read_number(prop, na); if(base_addr && !(base_addr & ((0x1U << 12) - 1))) (void)of_iomap(np, 0); else hwadp_printf("hwad:reg addr = 0x%X Address of zero or that ones not aligned for page are not map!\n",base_addr); if(retval) ip_type = ~0U; retval = bsp_hwadp_register_base_addr(ip_type, (const char *)np->name, (void *)base_addr); if(retval) hwadp_printf("hwadp:failed to register base addr!ip_type=%d base_addr=%p name=%s\n",(int)ip_type, (void*)base_addr,np->name); continue; } /* try to obtain irq number */ retval = of_property_read_u32_index(np, "interrupts", 1, &irq_num); if(retval) continue; retval = of_property_read_u32(np, "int_type", &int_type); if(retval) int_type = ~0U; if(bsp_hwadp_register_irq_num(int_type, (const char *)np->name, irq_num)) hwadp_printf("hwadp:failed to register irq number!int_type=%d irq_num=%d name=%s\n", (int)int_type, irq_num, np->name); }
/** * of_irq_parse_one - Resolve an interrupt for a device * @device: the device whose interrupt is to be resolved * @index: index of the interrupt to resolve * @out_irq: structure of_irq filled by this function * * This function resolves an interrupt for a node by walking the interrupt tree, * finding which interrupt controller node it is attached to, and returning the * interrupt specifier that can be used to retrieve a Linux IRQ number. */ int of_irq_parse_one(struct device_node *device, int index, struct of_phandle_args *out_irq) { struct device_node *p; const __be32 *addr; u32 intsize; int i, res; pr_debug("of_irq_parse_one: dev=%pOF, index=%d\n", device, index); /* OldWorld mac stuff is "special", handle out of line */ if (of_irq_workarounds & OF_IMAP_OLDWORLD_MAC) return of_irq_parse_oldworld(device, index, out_irq); /* Get the reg property (if any) */ addr = of_get_property(device, "reg", NULL); /* Try the new-style interrupts-extended first */ res = of_parse_phandle_with_args(device, "interrupts-extended", "#interrupt-cells", index, out_irq); if (!res) return of_irq_parse_raw(addr, out_irq); /* Look for the interrupt parent. */ p = of_irq_find_parent(device); if (p == NULL) return -EINVAL; /* Get size of interrupt specifier */ if (of_property_read_u32(p, "#interrupt-cells", &intsize)) { res = -EINVAL; goto out; } pr_debug(" parent=%pOF, intsize=%d\n", p, intsize); /* Copy intspec into irq structure */ out_irq->np = p; out_irq->args_count = intsize; for (i = 0; i < intsize; i++) { res = of_property_read_u32_index(device, "interrupts", (index * intsize) + i, out_irq->args + i); if (res) goto out; } pr_debug(" intspec=%d\n", *out_irq->args); /* Check if there are any interrupt-map translations to process */ res = of_irq_parse_raw(addr, out_irq); out: of_node_put(p); return res; }
static int arizona_of_get_micd_ranges(struct arizona *arizona, const char *prop) { int nranges; int i, j; int ret = 0; u32 value; struct arizona_micd_range *micd_ranges; nranges = arizona_of_get_u32_num_groups(arizona, prop, 2); if (nranges < 0) return nranges; micd_ranges = devm_kzalloc(arizona->dev, nranges * sizeof(struct arizona_micd_range), GFP_KERNEL); for (i = 0, j = 0; i < nranges; ++i) { ret = of_property_read_u32_index(arizona->dev->of_node, prop, j++, &value); if (ret < 0) goto error; micd_ranges[i].max = value; ret = of_property_read_u32_index(arizona->dev->of_node, prop, j++, &value); if (ret < 0) goto error; micd_ranges[i].key = value; } arizona->pdata.micd_ranges = micd_ranges; arizona->pdata.num_micd_ranges = nranges; return ret; error: devm_kfree(arizona->dev, micd_ranges); dev_err(arizona->dev, "DT property %s is malformed: %d\n", prop, ret); return ret; }
static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev) { struct device_node *np = dev->of_node; struct regmap *sys_mgr_base_addr; u32 reg_offset, reg_shift; int ret; dwmac->stmmac_rst = devm_reset_control_get(dev, STMMAC_RESOURCE_NAME); if (IS_ERR(dwmac->stmmac_rst)) { dev_info(dev, "Could not get reset control!\n"); return -EINVAL; } dwmac->interface = of_get_phy_mode(np); sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); if (IS_ERR(sys_mgr_base_addr)) { dev_info(dev, "No sysmgr-syscon node found\n"); return PTR_ERR(sys_mgr_base_addr); } ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); if (ret) { dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n"); return -EINVAL; } ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); if (ret) { dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n"); return -EINVAL; } dwmac->reg_offset = reg_offset; dwmac->reg_shift = reg_shift; dwmac->sys_mgr_base_addr = sys_mgr_base_addr; dwmac->dev = dev; return 0; }
int of_at91_get_clk_range(struct device_node *np, const char *propname, struct clk_range *range) { u32 min, max; int ret; ret = of_property_read_u32_index(np, propname, 0, &min); if (ret) return ret; ret = of_property_read_u32_index(np, propname, 1, &max); if (ret) return ret; if (range) { range->min = min; range->max = max; } return 0; }
static void MtkInterfaceConfigParse(struct device_node *node) { if (of_property_read_u32_index(node, AUDDRV_AUD_CLKGPIO, 0, &(Auddrv_CLK_Setting[Auddrv_CLK_Mosi].Gpio_Number))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_AUD_CLKGPIO); } if (of_property_read_u32_index(node, AUDDRV_AUD_CLKGPIO, 1, &(Auddrv_CLK_Setting[Auddrv_CLK_Mosi].Gpio_Mode))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_AUD_CLKGPIO); } if (of_property_read_u32_index(node, AUDDRV_AUD_DATIGPIO, 0, &(Auddrv_CLK_Setting[Auddrv_DataIn1_Mosi].Gpio_Number))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_AUD_DATIGPIO); } if (of_property_read_u32_index(node, AUDDRV_AUD_DATIGPIO, 1, &(Auddrv_CLK_Setting[Auddrv_DataIn1_Mosi].Gpio_Mode))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_AUD_DATIGPIO); } if (of_property_read_u32_index(node, AUDDRV_AUD_DATOGPIO, 0, &(Auddrv_CLK_Setting[Auddrv_DataOut1_Mosi].Gpio_Number))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_AUD_DATOGPIO); } if (of_property_read_u32_index(node, AUDDRV_AUD_DATOGPIO, 1, &(Auddrv_CLK_Setting[Auddrv_DataOut1_Mosi].Gpio_Mode))) { printk("%s %s not exist!!!\n", __func__, AUDDRV_AUD_DATOGPIO); } }
void bsp_abb_deassert_reset(void) { struct device_node *dev = NULL; const char *name = "hisilicon,abb_balong_mdm_for_sysc"; static u32 addr = 0; static u32 offset = 0; if (!g_abb_inited) { dev = of_find_compatible_node(NULL, NULL, name); if(NULL == dev) { bsp_trace(BSP_LOG_LEVEL_ERROR, BSP_MODU_ABB, "ABB device node not found\n"); return; } of_property_read_u32_index(dev, "abb_srst_dis", 0, &addr); of_property_read_u32_index(dev, "abb_srst_dis", 1, &offset); if (addr) addr = (u32)bsp_sysctrl_addr_get((void *)addr); } if (addr) writel(0x01U << offset, addr); }
static int __init nvadsp_parse_dt(struct platform_device *pdev) { struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; u32 *adsp_reset; u32 *adsp_mem; int iter; adsp_reset = drv_data->unit_fpga_reset; adsp_mem = drv_data->adsp_mem; for (iter = 0; iter < ADSP_MEM_END; iter++) { if (of_property_read_u32_index(dev->of_node, "nvidia,adsp_mem", iter, &adsp_mem[iter])) { dev_err(dev, "adsp memory dt %d not found\n", iter); return -EINVAL; } } drv_data->adsp_unit_fpga = of_property_read_bool(dev->of_node, "nvidia,adsp_unit_fpga"); if (drv_data->adsp_unit_fpga) { for (iter = 0; iter < ADSP_UNIT_FPGA_RESET_END; iter++) { if (of_property_read_u32_index(dev->of_node, "nvidia,adsp_unit_fpga_reset", iter, &adsp_reset[iter])) { dev_err(dev, "adsp reset dt %d not found\n", iter); return -EINVAL; } } } nvadsp_parse_clk_entries(pdev); return 0; }
static int nvaudio_ivc_init(struct nvaudio_ivc_ctxt *ictxt) { int err, ivc_queue; struct device_node *dn, *hv_dn; struct device *dev = ictxt->dev; struct tegra_hv_ivc_cookie *ivck = NULL; dn = dev->of_node; if (dn == NULL) { dev_err(dev, "No OF data\n"); return -EINVAL; } hv_dn = of_parse_phandle(dn, "ivc_queue", 0); if (hv_dn == NULL) { dev_err(dev, "Failed to parse phandle of ivc prop\n"); return -EINVAL; } err = of_property_read_u32_index(dn, "ivc_queue", 1, &ivc_queue); if (err != 0) { dev_err(dev, "Failed to read IVC property ID\n"); of_node_put(hv_dn); return -EINVAL; } ivck = tegra_hv_ivc_reserve(hv_dn, ivc_queue, NULL); if (IS_ERR_OR_NULL(ivck)) { dev_err(dev, "Failed to reserve ivc queue %d\n", ivc_queue); if (ivck == ERR_PTR(-EPROBE_DEFER)) return -EPROBE_DEFER; else return -EINVAL; } of_node_put(hv_dn); err = request_threaded_irq(ivck->irq, nvaudio_ivc_isr, NULL, 0, dev_name(dev), ictxt); if (err) { tegra_hv_ivc_unreserve(ivck); return -EINVAL; } ictxt->ivc_queue = ivc_queue; ictxt->ivck = ivck; return 0; }
s32 coresight_perctrl2_memmap(void) { char* name = "coresight,extern-status"; struct device_node* perctrl2_node = NULL; unsigned int reg_data[2] = {0,}; perctrl2_node = of_find_compatible_node(NULL, NULL, name); if(NULL == perctrl2_node) { cs_error("perctrl2_node error: of_find_compatible_node failed.\r\n"); return BSP_ERROR; } if(of_property_read_u32_array(perctrl2_node, "reg", reg_data, 2)) { cs_error(" cs get dts reg error\n"); return BSP_ERROR; } g_perctrl2_reg.phy_addr = reg_data[0]; g_perctrl2_reg.virt_addr = bsp_sysctrl_addr_get((void*)reg_data[0]); (void)of_property_read_u32_index(perctrl2_node, "offset", 0,&g_perctrl2_reg.offset); (void)of_property_read_u32_index(perctrl2_node, "pclkdbg_clkoff_sys", 0,&g_perctrl2_reg.pclkdbg_clkoff_sys); (void)of_property_read_u32_index(perctrl2_node, "atclkoff_sys", 0,&g_perctrl2_reg.atclkoff_sys); (void)of_property_read_u32_index(perctrl2_node, "pclkdbg_to_modem_clk_off_sys", 0,&g_perctrl2_reg.pclkdbg_to_modem_clk_off_sys); (void)of_property_read_u32_index(perctrl2_node, "atclk_to_modem_clkoff_sys", 0,&g_perctrl2_reg.atclk_to_modem_clkoff_sys); (void)of_property_read_u32_index(perctrl2_node, "modem_cssys_rst_req", 0,&g_perctrl2_reg.modem_cssys_rst_req); cs_error("phy_addr = 0x%x,virt_addr = 0x%x,g_perctrl2_reg.offset = 0x%x\n",g_perctrl2_reg.phy_addr ,g_perctrl2_reg.virt_addr,g_perctrl2_reg.offset ); cs_error("pclkdbg_clkoff_sys = 0x%x\n",g_perctrl2_reg.pclkdbg_clkoff_sys); cs_error("atclkoff_sys = 0x%x\n",g_perctrl2_reg.atclkoff_sys); cs_error("pclkdbg_to_modem_clk_off_sys = 0x%x\n",g_perctrl2_reg.pclkdbg_to_modem_clk_off_sys); cs_error("modem_cssys_rst_req = 0x%x\n",g_perctrl2_reg.modem_cssys_rst_req ); cs_error("atclk_to_modem_clkoff_sys = 0x%x\n",g_perctrl2_reg.atclk_to_modem_clkoff_sys); return BSP_OK; }
void sci_parse_ap_sys_ctrl(SCI_CFG_STRU * p_sci_cfg) { if(p_sci_cfg == NULL) { return; } const char* name = "hisilicon,sci_sys_ctrl"; struct device_node* node = NULL; node = of_find_compatible_node(NULL,NULL,name); if(node == NULL) { p_sci_cfg->sci_sys_ctrl.ap_sci_sys_flag = AP_SCI_SYS_UNUSE; return; } (void)of_property_read_u32_index(node, "use_flag", 0,&p_sci_cfg->sci_sys_ctrl.ap_sci_sys_flag); if(p_sci_cfg->sci_sys_ctrl.ap_sci_sys_flag == AP_SCI_SYS_UNUSE) { sci_print("this product no need operate ip\n"); return; } (void)of_property_read_u32_index(node, "sys_ctrl_base_addr", 0,&p_sci_cfg->sci_sys_ctrl.phy_addr); if(p_sci_cfg->sci_sys_ctrl.phy_addr != 0) { p_sci_cfg->sci_sys_ctrl.virt_addr = bsp_sysctrl_addr_get((void*)p_sci_cfg->sci_sys_ctrl.phy_addr); } else { p_sci_cfg->sci_sys_ctrl.ap_sci_sys_flag = AP_SCI_SYS_UNUSE; sci_print("phy addr id null\n"); return; } if(p_sci_cfg->sci_sys_ctrl.virt_addr == NULL) { p_sci_cfg->sci_sys_ctrl.ap_sci_sys_flag = AP_SCI_SYS_UNUSE; sci_print("virt addr id null\n"); return; } (void)of_property_read_u32_index(node, "sys_ctrl_sci_iprst", 0,&p_sci_cfg->sci_sys_ctrl.sci_rst_reg_off); (void)of_property_read_u32_index(node, "sys_ctrl_sci_ipunrst", 0,&p_sci_cfg->sci_sys_ctrl.sci_unrst_reg_off); (void)of_property_read_u32_index(node, "sys_ctrl_sci0_bit_off", 0,&p_sci_cfg->sci_sys_ctrl.sci0_bit_off); (void)of_property_read_u32_index(node, "sys_ctrl_sci1_bit_off", 0,&p_sci_cfg->sci_sys_ctrl.sci1_bit_off); }
/** * ti_abb_init_table() - Initialize ABB table from device tree * @dev: device * @abb: pointer to the abb instance * @rinit_data: regulator initdata * * Return: 0 on success or appropriate error value when fails */ static int ti_abb_init_table(struct device *dev, struct ti_abb *abb, struct regulator_init_data *rinit_data) { struct ti_abb_info *info; const u32 num_values = 6; char *pname = "ti,abb_info"; u32 i; unsigned int *volt_table; int num_entries, min_uV = INT_MAX, max_uV = 0; struct regulation_constraints *c = &rinit_data->constraints; /* * Each abb_info is a set of n-tuple, where n is num_values, consisting * of voltage and a set of detection logic for ABB information for that * voltage to apply. */ num_entries = of_property_count_u32_elems(dev->of_node, pname); if (num_entries < 0) { dev_err(dev, "No '%s' property?\n", pname); return num_entries; } if (!num_entries || (num_entries % num_values)) { dev_err(dev, "All '%s' list entries need %d vals\n", pname, num_values); return -EINVAL; } num_entries /= num_values; info = devm_kzalloc(dev, sizeof(*info) * num_entries, GFP_KERNEL); if (!info) return -ENOMEM; abb->info = info; volt_table = devm_kzalloc(dev, sizeof(unsigned int) * num_entries, GFP_KERNEL); if (!volt_table) return -ENOMEM; abb->rdesc.n_voltages = num_entries; abb->rdesc.volt_table = volt_table; /* We do not know where the OPP voltage is at the moment */ abb->current_info_idx = -EINVAL; for (i = 0; i < num_entries; i++, info++, volt_table++) { u32 efuse_offset, rbb_mask, fbb_mask, vset_mask; u32 efuse_val; /* NOTE: num_values should equal to entries picked up here */ of_property_read_u32_index(dev->of_node, pname, i * num_values, volt_table); of_property_read_u32_index(dev->of_node, pname, i * num_values + 1, &info->opp_sel); of_property_read_u32_index(dev->of_node, pname, i * num_values + 2, &efuse_offset); of_property_read_u32_index(dev->of_node, pname, i * num_values + 3, &rbb_mask); of_property_read_u32_index(dev->of_node, pname, i * num_values + 4, &fbb_mask); of_property_read_u32_index(dev->of_node, pname, i * num_values + 5, &vset_mask); dev_dbg(dev, "[%d]v=%d ABB=%d ef=0x%x rbb=0x%x fbb=0x%x vset=0x%x\n", i, *volt_table, info->opp_sel, efuse_offset, rbb_mask, fbb_mask, vset_mask); /* Find min/max for voltage set */ if (min_uV > *volt_table) min_uV = *volt_table; if (max_uV < *volt_table) max_uV = *volt_table; if (!abb->efuse_base) { /* Ignore invalid data, but warn to help cleanup */ if (efuse_offset || rbb_mask || fbb_mask || vset_mask) dev_err(dev, "prop '%s': v=%d,bad efuse/mask\n", pname, *volt_table); goto check_abb; } efuse_val = readl(abb->efuse_base + efuse_offset); /* Use ABB recommendation from Efuse */ if (efuse_val & rbb_mask) info->opp_sel = TI_ABB_SLOW_OPP; else if (efuse_val & fbb_mask) info->opp_sel = TI_ABB_FAST_OPP; else if (rbb_mask || fbb_mask) info->opp_sel = TI_ABB_NOMINAL_OPP; dev_dbg(dev, "[%d]v=%d efusev=0x%x final ABB=%d\n", i, *volt_table, efuse_val, info->opp_sel); /* Use recommended Vset bits from Efuse */ if (!abb->ldo_base) { if (vset_mask) dev_err(dev, "prop'%s':v=%d vst=%x LDO base?\n", pname, *volt_table, vset_mask); continue; } info->vset = (efuse_val & vset_mask) >> __ffs(vset_mask); dev_dbg(dev, "[%d]v=%d vset=%x\n", i, *volt_table, info->vset); check_abb: switch (info->opp_sel) { case TI_ABB_NOMINAL_OPP: case TI_ABB_FAST_OPP: case TI_ABB_SLOW_OPP: /* Valid values */ break; default: dev_err(dev, "%s:[%d]v=%d, ABB=%d is invalid! Abort!\n", __func__, i, *volt_table, info->opp_sel); return -EINVAL; } } /* Setup the min/max voltage constraints from the supported list */ c->min_uV = min_uV; c->max_uV = max_uV; return 0; }