void __init mv64x60_init_irq(void) { struct device_node *np; phys_addr_t paddr; unsigned int size; const unsigned int *reg; unsigned long flags; np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp"); reg = of_get_property(np, "reg", &size); paddr = of_translate_address(np, reg); mv64x60_gpp_reg_base = ioremap(paddr, reg[1]); of_node_put(np); np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-pic"); reg = of_get_property(np, "reg", &size); paddr = of_translate_address(np, reg); mv64x60_irq_reg_base = ioremap(paddr, reg[1]); mv64x60_irq_host = irq_domain_add_linear(np, MV64x60_NUM_IRQS, &mv64x60_host_ops, NULL); spin_lock_irqsave(&mv64x60_lock, flags); out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK, mv64x60_cached_gpp_mask); out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO, mv64x60_cached_low_mask); out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI, mv64x60_cached_high_mask); out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE, 0); out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_LO, 0); out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_HI, 0); spin_unlock_irqrestore(&mv64x60_lock, flags); }
static void __init c2k_setup_arch(void) { struct device_node *np; phys_addr_t paddr; const unsigned int *reg; /* * ioremap mpp and gpp registers in case they are later * needed by c2k_reset_board(). */ np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-mpp"); reg = of_get_property(np, "reg", NULL); paddr = of_translate_address(np, reg); of_node_put(np); mv64x60_mpp_reg_base = ioremap(paddr, reg[1]); np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp"); reg = of_get_property(np, "reg", NULL); paddr = of_translate_address(np, reg); of_node_put(np); mv64x60_gpp_reg_base = ioremap(paddr, reg[1]); #ifdef CONFIG_PCI mv64x60_pci_init(); #endif }
static void __init prpmc2800_setup_arch(void) { struct device_node *np; phys_addr_t paddr; const unsigned int *reg; /* */ np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-mpp"); reg = of_get_property(np, "reg", NULL); paddr = of_translate_address(np, reg); of_node_put(np); mv64x60_mpp_reg_base = ioremap(paddr, reg[1]); np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp"); reg = of_get_property(np, "reg", NULL); paddr = of_translate_address(np, reg); of_node_put(np); mv64x60_gpp_reg_base = ioremap(paddr, reg[1]); #ifdef CONFIG_PCI mv64x60_pci_init(); #endif printk("Motorola %s\n", prpmc2800_platform_name); }
static int __init add_legacy_soc_port(struct device_node *np, struct device_node *soc_dev) { u64 addr; const u32 *addrp; upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; struct device_node *tsi = of_get_parent(np); /* We only support ports that have a clock frequency properly * encoded in the device-tree. */ if (get_property(np, "clock-frequency", NULL) == NULL) return -1; /* if rtas uses this device, don't try to use it as well */ if (get_property(np, "used-by-rtas", NULL) != NULL) return -1; /* Get the address */ addrp = of_get_address(soc_dev, 0, NULL, NULL); if (addrp == NULL) return -1; addr = of_translate_address(soc_dev, addrp); if (addr == OF_BAD_ADDR) return -1; /* Add port, irq will be dealt with later. We passed a translated * IO port value. It will be fixed up later along with the irq */ if (tsi && !strcmp(tsi->type, "tsi-bridge")) return add_legacy_port(np, -1, UPIO_TSI, addr, addr, NO_IRQ, flags, 0); else return add_legacy_port(np, -1, UPIO_MEM, addr, addr, NO_IRQ, flags, 0); }
/* * Interrupt setup and service. Interrrupts on the linkstation come * from the four PCI slots plus onboard 8241 devices: I2C, DUART. */ static void __init linkstation_init_IRQ(void) { struct mpic *mpic; struct device_node *dnp; void *prop; int size; phys_addr_t paddr; dnp = of_find_node_by_type(NULL, "open-pic"); if (dnp == NULL) return; prop = (struct device_node *)get_property(dnp, "reg", &size); paddr = (phys_addr_t)of_translate_address(dnp, prop); mpic = mpic_alloc(dnp, paddr, MPIC_PRIMARY | MPIC_WANTS_RESET, 4, 32, " EPIC "); BUG_ON(mpic == NULL); /* PCI IRQs */ mpic_assign_isu(mpic, 0, paddr + 0x10200); /* I2C */ mpic_assign_isu(mpic, 1, paddr + 0x11000); /* ttyS0, ttyS1 */ mpic_assign_isu(mpic, 2, paddr + 0x11100); mpic_init(mpic); }
u64 of_translate_dcr_address(struct device_node *dev, unsigned int dcr_n, unsigned int *out_stride) { struct device_node *dp; u32 *p; unsigned int stride; u64 ret; dp = find_dcr_parent(dev); if (dp == NULL) return OF_BAD_ADDR; /* Stride is not properly defined yet, default to 0x10 for Axon */ p = (u32 *)get_property(dp, "dcr-mmio-stride", NULL); stride = (p == NULL) ? 0x10 : *p; /* XXX FIXME: Which property name is to use of the 2 following ? */ p = (u32 *)get_property(dp, "dcr-mmio-range", NULL); if (p == NULL) p = (u32 *)get_property(dp, "dcr-mmio-space", NULL); if (p == NULL) return OF_BAD_ADDR; /* Maybe could do some better range checking here */ ret = of_translate_address(dp, p); if (ret != OF_BAD_ADDR) ret += (u64)(stride) * (u64)dcr_n; if (out_stride) *out_stride = stride; return ret; }
void of_device_make_bus_id(struct of_device *dev) { static atomic_t bus_no_reg_magic; struct device_node *node = dev->dev.of_node; const u32 *reg; u64 addr; int magic; /* * For MMIO, get the physical address */ reg = of_get_property(node, "reg", NULL); if (reg) { addr = of_translate_address(node, reg); if (addr != OF_BAD_ADDR) { dev_set_name(&dev->dev, "%llx.%s", (unsigned long long)addr, node->name); return; } } /* * No BusID, use the node name and add a globally incremented * counter (and pray...) */ magic = atomic_add_return(1, &bus_no_reg_magic); dev_set_name(&dev->dev, "%s.%d", node->name, magic - 1); }
int bman_init_ccsr(const struct device_node *node) { static int ccsr_map_fd; uint64_t phys_addr; const uint32_t *bman_addr; uint64_t regs_size; bman_addr = of_get_address(node, 0, ®s_size, NULL); if (!bman_addr) { pr_err("of_get_address cannot return BMan address"); return -EINVAL; } phys_addr = of_translate_address(node, bman_addr); if (!phys_addr) { pr_err("of_translate_address failed"); return -EINVAL; } ccsr_map_fd = open(BMAN_CCSR_MAP, O_RDWR); if (unlikely(ccsr_map_fd < 0)) { pr_err("Can not open /dev/mem for BMan CCSR map"); return ccsr_map_fd; } bman_ccsr_map = mmap(NULL, regs_size, PROT_READ | PROT_WRITE, MAP_SHARED, ccsr_map_fd, phys_addr); if (bman_ccsr_map == MAP_FAILED) { pr_err("Can not map BMan CCSR base Bman: " "0x%x Phys: 0x%lx size 0x%lx", *bman_addr, phys_addr, regs_size); return -EINVAL; } return 0; }
static int __of_address_to_resource(struct device_node *dev, const __be32 *addrp, u64 size, unsigned int flags, const char *name, struct resource *r) { u64 taddr; if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0) return -EINVAL; taddr = of_translate_address(dev, addrp); if (taddr == OF_BAD_ADDR) return -EINVAL; memset(r, 0, sizeof(struct resource)); if (flags & IORESOURCE_IO) { unsigned long port; port = pci_address_to_pio(taddr); if (port == (unsigned long)-1) return -EINVAL; r->start = port; r->end = port + size - 1; } else { r->start = taddr; r->end = taddr + size - 1; } r->flags = flags; r->name = name ? name : dev->full_name; return 0; }
/*Add Device tree for ramoops, linux patch 2fddba4..1d43305 ++ */ static int __init of_ramoops_platform_data(struct device_node *node, struct ramoops_platform_data *pdata) { const __be32 *addrp; const __be32 *prop; u64 size; memset(pdata, 0, sizeof(*pdata)); addrp = of_get_address(node, 0, &size, NULL); if (addrp == NULL) return -EINVAL; pdata->mem_address = of_translate_address(node, addrp); pdata->mem_size = size; prop = of_get_property(node, "record-size", NULL); if (!prop) return -EINVAL; pdata->record_size = be32_to_cpup(prop); prop = of_get_property(node, "console-size", NULL); if (!prop) return -EINVAL; pdata->console_size = be32_to_cpup(prop); prop = of_get_property(node, "ftrace-size", NULL); if (!prop) return -EINVAL; pdata->ftrace_size = be32_to_cpup(prop); prop = of_get_property(node, "dump-oops", NULL); if (!prop) return -EINVAL; pdata->dump_oops = be32_to_cpup(prop); return 0; }
/** * of_device_make_bus_id - Use the device node data to assign a unique name * @dev: pointer to device structure that is linked to a device tree node * * This routine will first try using the translated bus address to * derive a unique name. If it cannot, then it will prepend names from * parent nodes until a unique name can be derived. */ void of_device_make_bus_id(struct device *dev) { struct device_node *node = dev->of_node; const __be32 *reg; u64 addr; /* Construct the name, using parent nodes if necessary to ensure uniqueness */ while (node->parent) { /* * If the address can be translated, then that is as much * uniqueness as we need. Make it the first component and return */ reg = of_get_property(node, "reg", NULL); if (reg && (addr = of_translate_address(node, reg)) != OF_BAD_ADDR) { dev_set_name(dev, dev_name(dev) ? "%llx.%s:%s" : "%llx.%s", (unsigned long long)addr, node->name, dev_name(dev)); return; } /* format arguments only used if dev_name() resolves to NULL */ dev_set_name(dev, dev_name(dev) ? "%s:%s" : "%s", strrchr(node->full_name, '/') + 1, dev_name(dev)); node = node->parent; } }
phys_addr_t get_immrbase(void) { struct device_node *soc; if (immrbase != -1) return immrbase; soc = of_find_node_by_type(NULL, "soc"); if (soc) { int size; u32 naddr; const __be32 *prop = of_get_property(soc, "#address-cells", &size); if (prop && size == 4) naddr = be32_to_cpup(prop); else naddr = 2; prop = of_get_property(soc, "ranges", &size); if (prop) immrbase = of_translate_address(soc, prop + naddr); of_node_put(soc); } return immrbase; }
int __init find_via_cuda(void) { struct adb_request req; phys_addr_t taddr; const u32 *reg; int err; if (vias != 0) return 1; vias = of_find_node_by_name(NULL, "via-cuda"); if (vias == 0) return 0; reg = get_property(vias, "reg", NULL); if (reg == NULL) { printk(KERN_ERR "via-cuda: No \"reg\" property !\n"); goto fail; } taddr = of_translate_address(vias, reg); if (taddr == 0) { printk(KERN_ERR "via-cuda: Can't translate address !\n"); goto fail; } via = ioremap(taddr, 0x2000); if (via == NULL) { printk(KERN_ERR "via-cuda: Can't map address !\n"); goto fail; } cuda_state = idle; sys_ctrler = SYS_CTRLER_CUDA; err = cuda_init_via(); if (err) { printk(KERN_ERR "cuda_init_via() failed\n"); via = NULL; return 0; } /* Clear and enable interrupts, but only on PPC. On 68K it's done */ /* for us by the main VIA driver in arch/m68k/mac/via.c */ #ifndef CONFIG_MAC out_8(&via[IFR], 0x7f); /* clear interrupts by writing 1s */ out_8(&via[IER], IER_SET|SR_INT); /* enable interrupt from SR */ #endif /* enable autopoll */ cuda_request(&req, NULL, 3, CUDA_PACKET, CUDA_AUTOPOLL, 1); while (!req.complete) cuda_poll(); return 1; fail: of_node_put(vias); vias = NULL; return 0; }
int __init find_via_cuda(void) { struct adb_request req; phys_addr_t taddr; const u32 *reg; int err; if (vias != 0) return 1; vias = of_find_node_by_name(NULL, "via-cuda"); if (vias == 0) return 0; reg = of_get_property(vias, "reg", NULL); if (reg == NULL) { printk(KERN_ERR "via-cuda: No \"reg\" property !\n"); goto fail; } taddr = of_translate_address(vias, reg); if (taddr == 0) { printk(KERN_ERR "via-cuda: Can't translate address !\n"); goto fail; } via = ioremap(taddr, 0x2000); if (via == NULL) { printk(KERN_ERR "via-cuda: Can't map address !\n"); goto fail; } cuda_state = idle; sys_ctrler = SYS_CTRLER_CUDA; err = cuda_init_via(); if (err) { printk(KERN_ERR "cuda_init_via() failed\n"); via = NULL; return 0; } out_8(&via[IFR], 0x7f); out_8(&via[IER], IER_SET|SR_INT); cuda_request(&req, NULL, 3, CUDA_PACKET, CUDA_AUTOPOLL, 1); while (!req.complete) cuda_poll(); return 1; fail: of_node_put(vias); vias = NULL; return 0; }
/** * of_device_make_bus_id - Use the device node data to assign a unique name * @dev: pointer to device structure that is linked to a device tree node * * This routine will first try using either the dcr-reg or the reg property * value to derive a unique name. As a last resort it will use the node * name followed by a unique number. */ void of_device_make_bus_id(struct device *dev) { static atomic_t bus_no_reg_magic; struct device_node *node = dev->of_node; const __be32 *reg; u64 addr; const __be32 *addrp; int magic; #ifdef CONFIG_PPC_DCR /* * If it's a DCR based device, use 'd' for native DCRs * and 'D' for MMIO DCRs. */ reg = of_get_property(node, "dcr-reg", NULL); if (reg) { #ifdef CONFIG_PPC_DCR_NATIVE dev_set_name(dev, "d%x.%s", *reg, node->name); #else /* CONFIG_PPC_DCR_NATIVE */ u64 addr = of_translate_dcr_address(node, *reg, NULL); if (addr != OF_BAD_ADDR) { dev_set_name(dev, "D%llx.%s", (unsigned long long)addr, node->name); return; } #endif /* !CONFIG_PPC_DCR_NATIVE */ } #endif /* CONFIG_PPC_DCR */ /* * For MMIO, get the physical address */ reg = of_get_property(node, "reg", NULL); if (reg) { if (of_can_translate_address(node)) { addr = of_translate_address(node, reg); } else { addrp = of_get_address(node, 0, NULL, NULL); if (addrp) addr = of_read_number(addrp, 1); else addr = OF_BAD_ADDR; } if (addr != OF_BAD_ADDR) { dev_set_name(dev, "%llx.%s", (unsigned long long)addr, node->name); return; } } /* * No BusID, use the node name and add a globally incremented * counter (and pray...) */ magic = atomic_add_return(1, &bus_no_reg_magic); dev_set_name(dev, "%s.%d", node->name, magic - 1); }
struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, struct of_pci_range *range) { const int na = 3, ns = 2; if (!range) return NULL; if (!parser->range || parser->range + parser->np > parser->end) return NULL; range->pci_space = parser->range[0]; range->flags = of_bus_pci_get_flags(parser->range); range->pci_addr = of_read_number(parser->range + 1, ns); range->cpu_addr = of_translate_address(parser->node, parser->range + na); range->size = of_read_number(parser->range + parser->pna + na, ns); parser->range += parser->np; /* Now consume following elements while they are contiguous */ while (parser->range + parser->np <= parser->end) { u32 flags, pci_space; u64 pci_addr, cpu_addr, size; pci_space = be32_to_cpup(parser->range); flags = of_bus_pci_get_flags(parser->range); pci_addr = of_read_number(parser->range + 1, ns); cpu_addr = of_translate_address(parser->node, parser->range + na); size = of_read_number(parser->range + parser->pna + na, ns); if (flags != range->flags) break; if (pci_addr != range->pci_addr + range->size || cpu_addr != range->cpu_addr + range->size) break; range->size += size; parser->range += parser->np; } return range; }
/* * Interrupt setup and service. Interrupts on the mpc7448_hpc2 come * from the four external INT pins, PCI interrupts are routed via * PCI interrupt control registers, it generates internal IRQ23 * * Interrupt routing on the Taiga Board: * TSI108:PB_INT[0] -> CPU0:INT# * TSI108:PB_INT[1] -> CPU0:MCP# * TSI108:PB_INT[2] -> N/C * TSI108:PB_INT[3] -> N/C */ static void __init mpc7448_hpc2_init_IRQ(void) { struct mpic *mpic; phys_addr_t mpic_paddr = 0; struct device_node *tsi_pic; #ifdef CONFIG_PCI unsigned int cascade_pci_irq; struct device_node *tsi_pci; struct device_node *cascade_node = NULL; #endif tsi_pic = of_find_node_by_type(NULL, "open-pic"); if (tsi_pic) { unsigned int size; const void *prop = of_get_property(tsi_pic, "reg", &size); mpic_paddr = of_translate_address(tsi_pic, prop); } if (mpic_paddr == 0) { printk("%s: No tsi108 PIC found !\n", __func__); return; } DBG("%s: tsi108 pic phys_addr = 0x%x\n", __func__, (u32) mpic_paddr); mpic = mpic_alloc(tsi_pic, mpic_paddr, MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET | MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108, 24, NR_IRQS-4, /* num_sources used */ "Tsi108_PIC"); BUG_ON(mpic == NULL); mpic_assign_isu(mpic, 0, mpic_paddr + 0x100); mpic_init(mpic); #ifdef CONFIG_PCI tsi_pci = of_find_node_by_type(NULL, "pci"); if (tsi_pci == NULL) { printk("%s: No tsi108 pci node found !\n", __func__); return; } cascade_node = of_find_node_by_type(NULL, "pic-router"); if (cascade_node == NULL) { printk("%s: No tsi108 pci cascade node found !\n", __func__); return; } cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0); DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, (u32) cascade_pci_irq); tsi108_pci_int_init(cascade_node); <<<<<<< HEAD
int cpm_muram_init(void) { struct device_node *np; struct resource r; u32 zero[OF_MAX_ADDR_CELLS] = {}; resource_size_t max = 0; int i = 0; int ret = 0; if (muram_pbase) return 0; spin_lock_init(&cpm_muram_lock); /* initialize the info header */ rh_init(&cpm_muram_info, 1, sizeof(cpm_boot_muram_rh_block) / sizeof(cpm_boot_muram_rh_block[0]), cpm_boot_muram_rh_block); np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data"); if (!np) { /* try legacy bindings */ np = of_find_node_by_name(NULL, "data-only"); if (!np) { printk(KERN_ERR "Cannot find CPM muram data node"); ret = -ENODEV; goto out; } } muram_pbase = of_translate_address(np, zero); if (muram_pbase == (phys_addr_t)OF_BAD_ADDR) { printk(KERN_ERR "Cannot translate zero through CPM muram node"); ret = -ENODEV; goto out; } while (of_address_to_resource(np, i++, &r) == 0) { if (r.end > max) max = r.end; rh_attach_region(&cpm_muram_info, r.start - muram_pbase, resource_size(&r)); } muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1); if (!muram_vbase) { printk(KERN_ERR "Cannot map CPM muram"); ret = -ENOMEM; } out: of_node_put(np); return ret; }
static void of_device_make_bus_id(struct of_device *dev) { static atomic_t bus_no_reg_magic; struct device_node *node = dev->node; char *name = dev->dev.bus_id; const u32 *reg; u64 addr; int magic; /* * If it's a DCR based device, use 'd' for native DCRs * and 'D' for MMIO DCRs. */ #ifdef CONFIG_PPC_DCR reg = of_get_property(node, "dcr-reg", NULL); if (reg) { #ifdef CONFIG_PPC_DCR_NATIVE snprintf(name, BUS_ID_SIZE, "d%x.%s", *reg, node->name); #else /* CONFIG_PPC_DCR_NATIVE */ addr = of_translate_dcr_address(node, *reg, NULL); if (addr != OF_BAD_ADDR) { snprintf(name, BUS_ID_SIZE, "D%llx.%s", (unsigned long long)addr, node->name); return; } #endif /* !CONFIG_PPC_DCR_NATIVE */ } #endif /* CONFIG_PPC_DCR */ /* * For MMIO, get the physical address */ reg = of_get_property(node, "reg", NULL); if (reg) { addr = of_translate_address(node, reg); if (addr != OF_BAD_ADDR) { snprintf(name, BUS_ID_SIZE, "%llx.%s", (unsigned long long)addr, node->name); return; } } /* * No BusID, use the node name and add a globally incremented * counter (and pray...) */ magic = atomic_add_return(1, &bus_no_reg_magic); snprintf(name, BUS_ID_SIZE, "%s.%d", node->name, magic - 1); }
/* * Retrieves and prepares the virtual address needed to access the hardware. */ static void __iomem *vi_setup_io_base(struct device_node *np) { phys_addr_t paddr; const unsigned int *reg; void *io_base = NULL; reg = of_get_property(np, "reg", NULL); if (reg) { paddr = of_translate_address(np, reg); if (paddr) io_base = ioremap(paddr, reg[1]); } return io_base; }
phys_addr_t get_csrbase(void) { struct device_node *tsi; if (tsi108_csr_base != -1) return tsi108_csr_base; tsi = of_find_node_by_type(NULL, "tsi-bridge"); if (tsi) { unsigned int size; const void *prop = of_get_property(tsi, "reg", &size); tsi108_csr_base = of_translate_address(tsi, prop); of_node_put(tsi); }; return tsi108_csr_base; }
void of_device_make_bus_id(struct device *dev) { static atomic_t bus_no_reg_magic; struct device_node *node = dev->of_node; const u32 *reg; u64 addr; const __be32 *addrp; int magic; #ifdef CONFIG_PPC_DCR reg = of_get_property(node, "dcr-reg", NULL); if (reg) { #ifdef CONFIG_PPC_DCR_NATIVE dev_set_name(dev, "d%x.%s", *reg, node->name); #else u64 addr = of_translate_dcr_address(node, *reg, NULL); if (addr != OF_BAD_ADDR) { dev_set_name(dev, "D%llx.%s", (unsigned long long)addr, node->name); return; } #endif } #endif reg = of_get_property(node, "reg", NULL); if (reg) { if (of_can_translate_address(node)) { addr = of_translate_address(node, reg); } else { addrp = of_get_address(node, 0, NULL, NULL); if (addrp) addr = of_read_number(addrp, 1); else addr = OF_BAD_ADDR; } if (addr != OF_BAD_ADDR) { dev_set_name(dev, "%llx.%s", (unsigned long long)addr, node->name); return; } } magic = atomic_add_return(1, &bus_no_reg_magic); dev_set_name(dev, "%s.%d", node->name, magic - 1); }
phys_addr_t get_qe_base(void) { struct device_node *qe; if (qebase != -1) return qebase; qe = of_find_node_by_type(NULL, "qe"); if (qe) { unsigned int size; const void *prop = of_get_property(qe, "reg", &size); qebase = of_translate_address(qe, prop); of_node_put(qe); }; return qebase; }
phys_addr_t get_immrbase(void) { struct device_node *soc; if (immrbase != -1) return immrbase; soc = of_find_node_by_type(NULL, "soc"); if (soc != 0) { unsigned int size; void *prop = get_property(soc, "reg", &size); immrbase = of_translate_address(soc, prop); of_node_put(soc); }; return immrbase; }
int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy, int index) { struct device_node *phynode = miphy_phy->phy->dev.of_node; const char *name; const __be32 *taddr; int type = miphy_phy->type; int ret; ret = of_property_read_string_index(phynode, "reg-names", index, &name); if (ret) { dev_err(dev, "no reg-names property not found\n"); return ret; } if (!strncmp(name, "syscfg", 6)) { taddr = of_get_address(phynode, index, NULL, NULL); if (!taddr) { dev_err(dev, "failed to fetch syscfg address\n"); return -EINVAL; } miphy_phy->ctrlreg = of_translate_address(phynode, taddr); if (miphy_phy->ctrlreg == OF_BAD_ADDR) { dev_err(dev, "failed to translate syscfg address\n"); return -EINVAL; } return 0; } if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) || (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE))) return 0; miphy_phy->base = of_iomap(phynode, index); if (!miphy_phy->base) { dev_err(dev, "Failed to map %s\n", phynode->full_name); return -EINVAL; } return 0; }
static int __init add_legacy_isa_port(struct device_node *np, struct device_node *isa_brg) { const u32 *reg; const char *typep; int index = -1; u64 taddr; DBG(" -> add_legacy_isa_port(%s)\n", np->full_name); /* Get the ISA port number */ reg = of_get_property(np, "reg", NULL); if (reg == NULL) return -1; /* Verify it's an IO port, we don't support anything else */ if (!(reg[0] & 0x00000001)) return -1; /* Now look for an "ibm,aix-loc" property that gives us ordering * if any... */ typep = of_get_property(np, "ibm,aix-loc", NULL); /* If we have a location index, then use it */ if (typep && *typep == 'S') index = simple_strtol(typep+1, NULL, 0) - 1; /* Translate ISA address. If it fails, we still register the port * with no translated address so that it can be picked up as an IO * port later by the serial driver */ taddr = of_translate_address(np, reg); if (taddr == OF_BAD_ADDR) taddr = 0; /* Add port, irq will be dealt with later */ return add_legacy_port(np, index, UPIO_PORT, reg[1], taddr, NO_IRQ, UPF_BOOT_AUTOCONF, 0); }
static void __iomem *offb_map_reg(struct device_node *np, int index, unsigned long offset, unsigned long size) { const u32 *addrp; u64 asize, taddr; unsigned int flags; addrp = of_get_pci_address(np, index, &asize, &flags); if (addrp == NULL) addrp = of_get_address(np, index, &asize, &flags); if (addrp == NULL) return NULL; if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0) return NULL; if ((offset + size) > asize) return NULL; taddr = of_translate_address(np, addrp); if (taddr == OF_BAD_ADDR) return NULL; return ioremap(taddr + offset, size); }
void holly_restart(char *cmd) { __be32 __iomem *ocn_bar1 = NULL; unsigned long bar; struct device_node *bridge = NULL; const void *prop; int size; phys_addr_t addr = 0xc0000000; local_irq_disable(); bridge = of_find_node_by_type(NULL, "tsi-bridge"); if (bridge) { prop = of_get_property(bridge, "reg", &size); addr = of_translate_address(bridge, prop); } addr += (TSI108_PB_OFFSET + 0x414); ocn_bar1 = ioremap(addr, 0x4); /* Turn on the BOOT bit so the addresses are correctly * routed to the HLP interface */ bar = ioread32be(ocn_bar1); bar |= 2; iowrite32be(bar, ocn_bar1); iosync(); /* Set SRR0 to the reset vector and turn on MSR_IP */ mtspr(SPRN_SRR0, 0xfff00100); mtspr(SPRN_SRR1, MSR_IP); /* Do an rfi to jump back to firmware. Somewhat evil, * but it works */ __asm__ __volatile__("rfi" : : : "memory"); /* Spin until reset happens. Shouldn't really get here */ for (;;) ; }
void __iomem * mpc52xx_find_and_map(const char *compatible) { struct device_node *ofn; const u32 *regaddr_p; u64 regaddr64, size64; ofn = of_find_compatible_node(NULL, NULL, compatible); if (!ofn) return NULL; regaddr_p = of_get_address(ofn, 0, &size64, NULL); if (!regaddr_p) { of_node_put(ofn); return NULL; } regaddr64 = of_translate_address(ofn, regaddr_p); of_node_put(ofn); return ioremap((u32)regaddr64, (u32)size64); }
phys_addr_t get_qe_base(void) { struct device_node *qe; int size; const u32 *prop; if (qebase != -1) return qebase; qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); if (!qe) { qe = of_find_node_by_type(NULL, "qe"); if (!qe) return qebase; } prop = of_get_property(qe, "reg", &size); if (prop && size >= sizeof(*prop)) qebase = of_translate_address(qe, prop); of_node_put(qe); return qebase; }