int __init omap3_s32k_init(void) { if(!omap35x_32k_synct_base) { omap35x_32k_synct_base = vmm_host_iomap(OMAP3_S32K_BASE, 0x1000); /* Enable I-clock for S32K */ omap3_cm_setbits(OMAP3_WKUP_CM, OMAP3_CM_ICLKEN_WKUP, OMAP3_CM_ICLKEN_WKUP_EN_32KSYNC_M); } return VMM_OK; }
void omap3_gpt_clock_enable(u32 gpt_num) { /* select clock source (1=sys_clk; 0=32K) for GPT */ if(omap3_gpt_config[gpt_num].src_sys_clk) { omap3_cm_setbits(omap3_gpt_config[gpt_num].cm_domain, OMAP3_CM_CLKSEL, omap3_gpt_config[gpt_num].clksel_mask); omap3_gpt_config[gpt_num].clk_hz = omap3_gpt_get_clk_speed(gpt_num); } else { omap3_cm_clrbits(omap3_gpt_config[gpt_num].cm_domain, OMAP3_CM_CLKSEL, omap3_gpt_config[gpt_num].clksel_mask); omap3_gpt_config[gpt_num].clk_hz = OMAP3_S32K_FREQ_HZ; } /* Enable I Clock for GPT */ omap3_cm_setbits(omap3_gpt_config[gpt_num].cm_domain, OMAP3_CM_ICLKEN, omap3_gpt_config[gpt_num].iclken_mask); /* Enable F Clock for GPT */ omap3_cm_setbits(omap3_gpt_config[gpt_num].cm_domain, OMAP3_CM_FCLKEN, omap3_gpt_config[gpt_num].fclken_mask); }