Example #1
0
void lcd_ctrl_init(void *lcdbase)
{
	struct prcm *prcm = (struct prcm *)PRCM_BASE;
	char *custom_lcd;
	char *displaytype = env_get("displaytype");

	if (displaytype == NULL)
		return;

	lcd_def = env_parse_displaytype(displaytype);
	/* If we did not recognize the preset, check if it's an env variable */
	if (lcd_def == NONE) {
		custom_lcd = env_get(displaytype);
		if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0)
			return;
	}

	panel_cfg.frame_buffer = lcdbase;
	omap3_dss_panel_config(&panel_cfg);
	/*
	 * Pixel clock is defined with many divisions and only few
	 * multiplications of the system clock. Since DSS FCLK divisor is set
	 * to 16 by default, we need to set it to a smaller value, like 3
	 * (chosen via trial and error).
	 */
	clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
}
Example #2
0
/*
 * Configure DSS to display background color on DVID
 * Configure VENC to display color bar on S-Video
 */
static void beagle_display_init(void)
{
	omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
	switch (get_board_revision()) {
	case REVISION_AXBX:
	case REVISION_CX:
	case REVISION_C4:
		omap3_dss_panel_config(&dvid_cfg);
		break;
	case REVISION_XM_AB:
	case REVISION_XM_C:
	default:
		omap3_dss_panel_config(&dvid_cfg_xm);
		break;
	}
}
void lcd_ctrl_init(void *lcdbase)
{
   sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
   sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
    
   udelay(200);
  
   omap3_dss_panel_config(&panel_info.dss_panel_config);
   omap3_dss_mem_config(&panel_info.dss_panel_config, lcdbase);
   lcd_set_base = lcdbase;
}
Example #4
0
void * video_hw_init(void) {
    //register GraphicDevice *pGD = (GraphicDevice *)&smi;
    struct panel_config pcfg;
/*    int hsw=0, hfp=0, hbp=0;
    int vsw=0, vfp=0, vbp=0;
    int lclk = 1, pclk=2, pol_flags = 0;
    int acbi = 0, acb = 0;*/
	int bpp = 0;
	struct ctfb_res_modes *res_mode;
	struct ctfb_res_modes var_mode;
        char * penv;
	pre_setup_video_env();
	if (NULL == (penv = getenv("ub_vid"))) return NULL;

	res_mode = (struct ctfb_res_modes *) &var_mode;
	bpp = video_get_params (res_mode, penv);

	smi.winSizeX = res_mode->xres;
	smi.winSizeY = res_mode->yres;
	smi.plnSizeX = res_mode->xres;
	smi.plnSizeY = res_mode->yres;

        smi.gdfBytesPP = bpp;
        if (2 == bpp) smi.gdfIndex = GDF_16BIT_565RGB;
        else if (1 == bpp) smi.gdfIndex = GDF__8BIT_332RGB;
        pcfg.panel_type = res_mode->vmode&1;

    pcfg.timing_h = TIMING(res_mode->hsync_len, res_mode->left_margin, res_mode->right_margin); //hsw, hfp, hbp);
    pcfg.timing_v = TIMING(res_mode->vsync_len, res_mode->upper_margin, res_mode->lower_margin); //vsw, vfp, vbp);
    pcfg.data_lines = 3;
    pcfg.lcd_size   = SIZE(smi.winSizeX, smi.winSizeY);
    pcfg.load_mode  = 0; //0x00000204 >> FRAME_MODE_SHIFT;
    smi.frameAdrs = LCD_VIDEO_ADDR;
    smi.memSize = smi.winSizeX * smi.winSizeY * smi.gdfBytesPP;
    pcfg.panel_color= 0;
    pcfg.divisor    = DIV(res_mode->pixclock >> 8, res_mode->pixclock & 0xff); //lclk, pclk);
    pcfg.pol_freq   = omapdss_set_pol_freq(res_mode->vmode >>1, res_mode->sync >> 8, res_mode->sync & 0xff); //pol_flags, acbi, acb); // 0, 0); //0x30000;
    //printf("Done w/ lcd init\n");
        /*if (!panel_cfg->panel_type)
	    pcfg.gfx_attrib = GFX_BURST(2) | GFX_FMT(RGB_16) //GFX_FMT(BMP_8) 
                    | GFX_EN;
        else*/
	    pcfg.gfx_attrib = GFX_BURST(2) | GFX_FMT(RGB_16) | GFX_EN;
    vidmem_clear(smi.frameAdrs, smi.winSizeX, smi.winSizeY, smi.gdfBytesPP);
    omap3_dss_panel_config(&pcfg);
    omap3_dss_enable();

    return ((void*)&smi);
}
Example #5
0
int board_video_init(void)
{
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
	void *fb;

	fb = (void *)FB_START_ADDRESS;

	lcd_cfg.frame_buffer = fb;

	setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
	setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);

	omap3_dss_panel_config(&lcd_cfg);
	omap3_dss_enable();

	return 0;
}
Example #6
0
int board_video_init(void)
{
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
	struct panel_config *panel = &lcd_cfg[0];
	char *s;
	u32 index = 0;

	void *fb;

	fb = (void *)0x88000000;

	s = env_get("panel");
	if (s) {
		index = simple_strtoul(s, NULL, 10);
		if (index < ARRAY_SIZE(lcd_cfg))
			panel = &lcd_cfg[index];
		else
			return 0;
	}

	panel->frame_buffer = fb;
	printf("Panel: %dx%d\n", panel_resolution[index].xres,
		panel_resolution[index].yres);
	panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
		(panel_resolution[index].xres - 1);

	gpio_request(LCD_PWR, "LCD Power");
	gpio_request(LCD_PON_PIN, "LCD Pon");
	gpio_direction_output(LCD_PWR, 0);
	gpio_direction_output(LCD_PON_PIN, 1);


	setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
	setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);

	omap3_dss_panel_config(panel);
	omap3_dss_enable();

	return 0;
}
Example #7
0
/*
 * Routine: misc_init_r
 * Description: Configure board specific parts
 */
int misc_init_r(void)
{
	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
	struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
	bool generate_fake_mac = false;
	u32 value;

	/* Enable i2c2 pullup resisters */
	value = readl(&prog_io_base->io1);
	value &= ~(PRG_I2C2_PULLUPRESX);
	writel(value, &prog_io_base->io1);

	printf("WINGZ energy \nIoT group \n CDAC Bangalore\n");
	setenv("musb", "musb_hdrc.fifo_mode=5");
	MUX_WINGZ_C();
	/* Set VAUX2 to 1.8V for EHCI PHY */
	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
					TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
					TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
					TWL4030_PM_RECEIVER_DEV_GRP_P1);
	

	
	if (expansion_config.content == 1)
		setenv(expansion_config.env_var, expansion_config.env_setting);

	twl4030_power_init();
	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
	

	/* Set GPIO states before they are made outputs */
	writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
		&gpio6_base->setdataout);
	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
		GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);

	/* Configure GPIOs to output */
	writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
	writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
		GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);

	dieid_num_r();

#ifdef CONFIG_VIDEO_OMAP3
	gpio_request(170, "dvi");
	gpio_direction_output(170, 0);
	gpio_set_value(170, 1);

	//beagle_display_init();
	omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
	omap3_dss_panel_config(&dvid_cfg);


	omap3_dss_enable();
#endif

#ifdef CONFIG_USB_MUSB_OMAP2PLUS
	musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
#endif

	if (generate_fake_mac) {
		u32 id[4];

		get_dieid(id);
		usb_fake_mac_from_die_id(id);
	}

	return 0;
}
Example #8
0
/*
 * Configure DSS to display background color on DVID
 * Configure VENC to display color bar on S-Video
 */
void blueshark_display_init(void)
{
	omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
	omap3_dss_panel_config(&dvid_cfg);
}