/* * ipipeif_set_stream - Enable/Disable streaming on the IPIPEIF module * @sd: ISP IPIPEIF V4L2 subdevice * @enable: Enable/disable stream */ static int ipipeif_set_stream(struct v4l2_subdev *sd, int enable) { struct iss_ipipeif_device *ipipeif = v4l2_get_subdevdata(sd); struct iss_device *iss = to_iss_device(ipipeif); struct iss_video *video_out = &ipipeif->video_out; int ret = 0; if (ipipeif->state == ISS_PIPELINE_STREAM_STOPPED) { if (enable == ISS_PIPELINE_STREAM_STOPPED) return 0; omap4iss_isp_subclk_enable(iss, IPIPEIF_DRV_SUBCLK_MASK); } switch (enable) { case ISS_PIPELINE_STREAM_CONTINUOUS: ipipeif_configure(ipipeif); ipipeif_print_status(ipipeif); /* * When outputting to memory with no buffer available, let the * buffer queue handler start the hardware. A DMA queue flag * ISS_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is * a buffer available. */ if (ipipeif->output & IPIPEIF_OUTPUT_MEMORY && !(video_out->dmaqueue_flags & ISS_VIDEO_DMAQUEUE_QUEUED)) break; atomic_set(&ipipeif->stopping, 0); if (ipipeif->output & IPIPEIF_OUTPUT_MEMORY) ipipeif_write_enable(ipipeif, 1); ipipeif_enable(ipipeif, 1); iss_video_dmaqueue_flags_clr(video_out); break; case ISS_PIPELINE_STREAM_STOPPED: if (ipipeif->state == ISS_PIPELINE_STREAM_STOPPED) return 0; if (omap4iss_module_sync_idle(&sd->entity, &ipipeif->wait, &ipipeif->stopping)) ret = -ETIMEDOUT; if (ipipeif->output & IPIPEIF_OUTPUT_MEMORY) ipipeif_write_enable(ipipeif, 0); ipipeif_enable(ipipeif, 0); omap4iss_isp_subclk_disable(iss, IPIPEIF_DRV_SUBCLK_MASK); iss_video_dmaqueue_flags_clr(video_out); break; } ipipeif->state = enable; return ret; }
/* * ipipe_set_stream - Enable/Disable streaming on the IPIPE module * @sd: ISP IPIPE V4L2 subdevice * @enable: Enable/disable stream */ static int ipipe_set_stream(struct v4l2_subdev *sd, int enable) { struct iss_ipipe_device *ipipe = v4l2_get_subdevdata(sd); struct iss_device *iss = to_iss_device(ipipe); int ret = 0; if (ipipe->state == ISS_PIPELINE_STREAM_STOPPED) { if (enable == ISS_PIPELINE_STREAM_STOPPED) return 0; omap4iss_isp_subclk_enable(iss, OMAP4_ISS_ISP_SUBCLK_IPIPE); /* Enable clk_arm_g0 */ iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_GCK_MMR, IPIPE_GCK_MMR_REG); /* Enable clk_pix_g[3:0] */ iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_GCK_PIX, IPIPE_GCK_PIX_G3 | IPIPE_GCK_PIX_G2 | IPIPE_GCK_PIX_G1 | IPIPE_GCK_PIX_G0); } switch (enable) { case ISS_PIPELINE_STREAM_CONTINUOUS: ipipe_configure(ipipe); ipipe_print_status(ipipe); atomic_set(&ipipe->stopping, 0); ipipe_enable(ipipe, 1); break; case ISS_PIPELINE_STREAM_STOPPED: if (ipipe->state == ISS_PIPELINE_STREAM_STOPPED) return 0; if (omap4iss_module_sync_idle(&sd->entity, &ipipe->wait, &ipipe->stopping)) ret = -ETIMEDOUT; ipipe_enable(ipipe, 0); omap4iss_isp_subclk_disable(iss, OMAP4_ISS_ISP_SUBCLK_IPIPE); break; } ipipe->state = enable; return ret; }