static void omap_pwm_led_set_pwm_cycle(struct omap_pwm_led *led, int cycle)
{
int n;
pr_debug("%s%s: \n", PASS1,__func__);
if (cycle == 0)
n = 0xff;
else n = cycle - 1;
if (cycle == LED_FULL) {
printk("!!!!!!!!!!cycle == LED_FULL \n");
omap_dm_timer_start(led->intensity_timer);
omap_dm_timer_set_pwm(led->intensity_timer, 1, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_set_match(led->intensity_timer, 1,
0xffffff00);
} else {
printk("!!!!!!!!!!cycle != LED_FULL, cycle=%i \n", cycle);
omap_dm_timer_start(led->intensity_timer);
omap_dm_timer_set_pwm(led->intensity_timer, 0, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_set_match(led->intensity_timer, 1,
(0xffffff00) | cycle);
}
}
static void omap_pwm_led_set_blink(struct omap_pwm_led *led)
{
pr_debug("%s%s: \n", PASS1,__func__);
if (!led->powered)
return;
if (led->on_period != 0 && led->off_period != 0) {
unsigned long load_reg, cmp_reg;
load_reg = 32768 * (led->on_period + led->off_period) / 1000;
cmp_reg = 32768 * led->on_period / 1000;
omap_dm_timer_stop(led->blink_timer);
omap_dm_timer_set_load(led->blink_timer, 1, -load_reg);
omap_dm_timer_set_match(led->blink_timer, 1, -cmp_reg);
omap_dm_timer_set_pwm(led->blink_timer, 1, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_write_counter(led->blink_timer, -2);
omap_dm_timer_start(led->blink_timer);
} else {
omap_dm_timer_set_pwm(led->blink_timer, 1, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_stop(led->blink_timer);
}
}
static void omap_pwm_led_set_pwm_cycle(struct omap_pwm_led *led, int cycle)
{
int pwm_frequency = 10000;
int def_on;
pr_debug("%s: cycle: %i\n",
__func__, cycle);
if (led->pdata->bkl_max)
cycle = ( (cycle * led->pdata->bkl_max ) / 255);
if (cycle < led->pdata->bkl_min)
cycle = led->pdata->bkl_min;
if (led->pdata->bkl_freq)
pwm_frequency = led->pdata->bkl_freq;
if (cycle != LED_FULL)
def_on = led->pdata->invert ? 1:0;
else
def_on = led->pdata->invert ? 0:1;
omap_dm_timer_set_pwm(led->intensity_timer, def_on, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
if (cycle != LED_FULL) {
pwm_set_speed(led->intensity_timer, pwm_frequency, 256-cycle);
omap_dm_timer_start(led->intensity_timer);
} else
omap_dm_timer_stop(led->intensity_timer);
}
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
PVR_ASSERT(psSysSpecData->psGPTimer == NULL);
/*
* This code could try requesting registers 9, 10, and 11,
* stopping at the first succesful request. We'll stick with
* 11 for now, as it avoids having to hard code yet more
* physical addresses into the code.
*/
psSysSpecData->psGPTimer = omap_dm_timer_request_specific(GPTIMER_TO_USE);
if (psSysSpecData->psGPTimer == NULL)
{
PVR_DPF((PVR_DBG_WARNING, "%s: omap_dm_timer_request_specific failed", __FUNCTION__));
return PVRSRV_ERROR_CLOCK_REQUEST_FAILED;
}
/* Set timer source to system clock */
omap_dm_timer_set_source(psSysSpecData->psGPTimer, OMAP_TIMER_SRC_SYS_CLK);
omap_dm_timer_enable(psSysSpecData->psGPTimer);
/* Set autoreload, and start value of 0 */
omap_dm_timer_set_load_start(psSysSpecData->psGPTimer, 1, 0);
omap_dm_timer_start(psSysSpecData->psGPTimer);
/*
* The DM timer API doesn't have a mechansim for obtaining the
* physical address of the counter register.
*/
psSysSpecData->sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE;
return PVRSRV_OK;
}
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
PVR_ASSERT(psSysSpecData->psGPTimer == NULL);
psSysSpecData->psGPTimer = omap_dm_timer_request_specific(GPTIMER_TO_USE);
if (psSysSpecData->psGPTimer == NULL)
{
PVR_DPF((PVR_DBG_WARNING, "%s: omap_dm_timer_request_specific failed", __FUNCTION__));
return PVRSRV_ERROR_CLOCK_REQUEST_FAILED;
}
omap_dm_timer_set_source(psSysSpecData->psGPTimer, OMAP_TIMER_SRC_SYS_CLK);
omap_dm_timer_enable(psSysSpecData->psGPTimer);
omap_dm_timer_set_load_start(psSysSpecData->psGPTimer, 1, 0);
omap_dm_timer_start(psSysSpecData->psGPTimer);
psSysSpecData->sTimerRegPhysBase.uiAddr = SYS_OMAP3_GPTIMER_REGS_SYS_PHYS_BASE;
return PVRSRV_OK;
}
int omap_rproc_activate(struct omap_device *od)
{
int i, ret = 0;
struct rproc *rproc = platform_get_drvdata(&od->pdev);
struct device *dev = rproc->dev;
struct omap_rproc_pdata *pdata = dev->platform_data;
struct omap_rproc_timers_info *timers = pdata->timers;
struct omap_rproc_priv *rpp = rproc->priv;
#ifdef CONFIG_REMOTE_PROC_AUTOSUSPEND
struct iommu *iommu;
if (!rpp->iommu) {
iommu = iommu_get(pdata->iommu_name);
if (IS_ERR(iommu)) {
dev_err(dev, "iommu_get error: %ld\n",
PTR_ERR(iommu));
return PTR_ERR(iommu);
}
rpp->iommu = iommu;
}
if (!rpp->mbox)
rpp->mbox = omap_mbox_get(pdata->sus_mbox_name, NULL);
#endif
/**
* explicitly configure a boot address from which remoteproc
* starts executing code when taken out of reset.
*/
_load_boot_addr(rproc, rpp->bootaddr);
/**
* Domain is in HW SUP thus in hw_auto but
* since remoteproc will be enabled clkdm
* needs to be in sw_sup (Do not let it idle).
*/
if (pdata->clkdm)
clkdm_wakeup(pdata->clkdm);
for (i = 0; i < pdata->timers_cnt; i++)
omap_dm_timer_start(timers[i].odt);
for (i = 0; i < od->hwmods_cnt; i++) {
ret = omap_hwmod_enable(od->hwmods[i]);
if (ret) {
for (i = 0; i < pdata->timers_cnt; i++)
omap_dm_timer_stop(timers[i].odt);
break;
}
}
/**
* Domain is in force_wkup but since remoteproc
* was enabled it is safe now to switch clkdm
* to hw_auto (let it idle).
*/
if (pdata->clkdm)
clkdm_allow_idle(pdata->clkdm);
return ret;
}
static ssize_t store_irblaster_freq(struct device *dev, struct device_attribute *attr,
const char* buf, size_t len)
{
frequency = simple_strtol(buf, NULL, 10);
/* Disable pwm */
if (frequency == 0) {
omap_dm_timer_stop(irb_pwm_timer);
omap_dm_timer_disable(irb_pwm_timer);
irb_state = 0;
return 0;
}
/* Enable pwm */
if (irb_state == 0) {
omap_dm_timer_enable(irb_pwm_timer);
omap_dm_timer_set_pwm(irb_pwm_timer, 0, 1, 2);
omap_dm_timer_start(irb_pwm_timer);
irb_state = 1;
}
pwm_set_speed(irb_pwm_timer, frequency, duty_cycle);
return len;
}
long hrt_ioctl(struct file* file,unsigned int cmd, unsigned long arg)
{
switch(cmd)
{
case CMD_START_TIMER:
if (!omap_dm_timer_start(timer))
{
return -EINVAL;
}
break;
case CMD_STOP_TIMER:
if (!omap_dm_timer_stop(timer))
{
return -EINVAL;
}
break;
case CMD_SET_TIMER_COUNTER_VALUE:
if(!omap_dm_timer_write_counter(timer,(int)arg))
{
return -EINVAL;
}
break;
default:
return -ENOTTY;
break;
}
return 0;
}
static int init_timing_params(struct lirc_rx51 *lirc_rx51)
{
u32 load, match;
load = -(lirc_rx51->fclk_khz * 1000 / lirc_rx51->freq);
match = -(lirc_rx51->duty_cycle * -load / 100);
omap_dm_timer_set_load(lirc_rx51->pwm_timer, 1, load);
omap_dm_timer_set_match(lirc_rx51->pwm_timer, 1, match);
omap_dm_timer_write_counter(lirc_rx51->pwm_timer, TIMER_MAX_VALUE - 2);
omap_dm_timer_start(lirc_rx51->pwm_timer);
omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer, 0);
omap_dm_timer_start(lirc_rx51->pulse_timer);
lirc_rx51->match = 0;
return 0;
}
static void sholest_lvibrator_power_on(void)
{
#ifdef CONFIG_VIB_PWM
gpio_set_value(SHOLEST_VIBRATOR_EN_GPIO, 1);
#endif
if (vib_pwm_timer == NULL)
sholest_lvibrator_initialization();
omap_dm_timer_enable(vib_pwm_timer);
omap_dm_timer_start(vib_pwm_timer);
}
static int __init gptimer_request_init(void)
{
struct clk *gt_fclk;
uint32_t gt_rate;
/*Requesting for any available timer*/
timer_ptr = omap_dm_timer_request();
if (timer_ptr == NULL) {
/*Timers are not available*/
printk(KERN_ERR "GPtimers are not available\n");
return -1;
}
switch (clock_type) {
case 1:
/*Set the clock source to 32Khz Clock*/
printk(KERN_INFO "Using OMAP_TIMER_SRC_32_KHZ source\n");
omap_dm_timer_set_source(timer_ptr,
OMAP_TIMER_SRC_32_KHZ);
break;
case 2:
/*Set the clock source to System Clock*/
printk(KERN_INFO "Using OMAP_TIMER_SRC_SYS_CLK source\n");
omap_dm_timer_set_source(timer_ptr,
OMAP_TIMER_SRC_SYS_CLK);
break;
case 3:
/*Set the clock source to System Clock*/
printk(KERN_INFO "Using OMAP_TIMER_SRC_EXT_CLK source\n");
omap_dm_timer_set_source(timer_ptr,
OMAP_TIMER_SRC_EXT_CLK);
break;
default:
printk(KERN_ERR "Invalid clock_type value. Use 1, 2 or 3\n");
return -1;
}
/*Figure out what IRQ our timer triggers*/
timer_irq = omap_dm_timer_get_irq(timer_ptr);
/*Get clock rate in Hz*/
gt_fclk = omap_dm_timer_get_fclk(timer_ptr);
gt_rate = clk_get_rate(gt_fclk);
/*Start the timer!*/
omap_dm_timer_start(timer_ptr);
printk(KERN_INFO "GP Timer initialized and started (%lu Hz, IRQ %d)\n",
(long unsigned)gt_rate, timer_irq);
return 0;
}
// Initialize the kernel module
static int __init gptimer_test_init(void)
{
int ret = 0;
struct clk *gt_fclk;
uint32_t gt_rate;
printk("gptimer test: starting moudle init\n");
// request a timer (we are asking for ANY open timer, see dmtimer.c for details on how this works)
timer_ptr = omap_dm_timer_request();
if(timer_ptr == NULL){
// oops, no timers available
printk("gptimer test: No more gp timers available, bailing out\n");
return -1;
}
// set the clock source to system clock
omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_SYS_CLK);
// set prescalar to 1:1
omap_dm_timer_set_prescaler(timer_ptr, 32);
// figure out what IRQ our timer triggers
timer_irq = omap_dm_timer_get_irq(timer_ptr);
// install our IRQ handler for our timer
ret = request_irq(timer_irq, timer_irq_handler, IRQF_DISABLED | IRQF_TIMER , "gptimer test", timer_irq_handler);
if(ret){
printk("gptimer test: request_irq failed (on irq %d), bailing out\n", timer_irq);
return ret;
}
// get clock rate in Hz
gt_fclk = omap_dm_timer_get_fclk(timer_ptr);
gt_rate = clk_get_rate(gt_fclk);
// set preload, and autoreload
// we set it to the clock rate in order to get 1 overflow every second
omap_dm_timer_set_load(timer_ptr, 1, 0xFFFFFFFF - gt_rate);
// setup timer to trigger our IRQ on the overflow event
omap_dm_timer_set_int_enable(timer_ptr, OMAP_TIMER_INT_OVERFLOW);
// start the timer!
omap_dm_timer_start(timer_ptr);
// done!
printk("gptimer test: GP Timer initialized and started (%lu Hz, IRQ %d)\n", (long unsigned)gt_rate, timer_irq);
// return sucsess
return 0;
}
static int panel_set_backlight_level(
struct omap_display *disp, int level)
{
int hw_level;
pr_debug("panel_set_backlight_level [%s] %d\n",
disp != NULL ? disp->panel->name: "cpt_wvga_48", level);
/* skip if panel is not on */
if (panel_state == 0) {
saved_bkl_level = level;
return 0;
}
/* clamp the level */
if (level < 0)
level = 0;
if (level > 255)
level = 255;
/* nothing to do if levels are equal */
if (bkl_level == level)
return 0;
/* stop backlight? */
if (level == 0) {
if (GPIO_EXISTS(display_gpio.bkl_pwon))
omap_set_gpio_dataout(GPIO_PIN(display_gpio.bkl_pwon), 0);
omap_dm_timer_stop(bkl_pwm);
omap_dm_timer_disable(bkl_pwm);
bkl_level = 0;
return 0;
}
/* start backlight? */
if (bkl_level == 0) {
omap_dm_timer_enable(bkl_pwm);
omap_dm_timer_set_pwm(bkl_pwm, 0, 1, 2);
omap_dm_timer_start(bkl_pwm);
if (GPIO_EXISTS(display_gpio.bkl_pwon))
omap_set_gpio_dataout(GPIO_PIN(display_gpio.bkl_pwon), 1);
}
/* set new level, g7 machines have inverted level */
hw_level = level;
if (!machine_is_archos_g6h())
hw_level = 255 - level;
pwm_set_speed(bkl_pwm, 10000, hw_level);
bkl_level = level;
return 0;
}
static void backlight_gptimer_update(struct omap_dss_device *dssdev)
{
struct ltn101al03 *lcd = dev_get_drvdata(&dssdev->dev);
omap_dm_timer_set_load(lcd->gptimer, 1, -PWM_DUTY_MAX);
omap_dm_timer_set_match(lcd->gptimer, 1, /* 0~25 */
-PWM_DUTY_MAX + lcd->current_brightness);
omap_dm_timer_set_pwm(lcd->gptimer, 0, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_enable(lcd->gptimer);
omap_dm_timer_write_counter(lcd->gptimer, -2);
omap_dm_timer_disable(lcd->gptimer);
omap_dm_timer_start(lcd->gptimer);
}
void pwm_gpt_start(int id)
{
if ( !_check_id(id) ) {
return;
}
if ( !_check_timer(id) ) {
return;
}
/* enable the timer, start the clock */
omap_dm_timer_enable(gpt_pwm_list[id].timer);
/* do not wait for ack, just set up the reg and leave */
/* this is better if you setup 2 correlated timers */
omap_dm_timer_start(gpt_pwm_list[id].timer);
}
/*!
******************************************************************************
@Function AcquireGPTimer
@Description Acquire a GP timer
@Return PVRSRV_ERROR
******************************************************************************/
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
PVR_ASSERT(psSysSpecData->psGPTimer == NULL);
/*
* This code has problems on module reload for OMAP5 running Linux
* 3.4.10, due to omap2_dm_timer_set_src (called by
* omap_dm_timer_request_specific), being unable to set the parent
* clock to OMAP_TIMER_SRC_32_KHZ.
* Not calling omap_dm_timer_set_source doesn't help.
*/
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) || !defined(MODULE)
/*
* This code could try requesting registers 9, 10, and 11,
* stopping at the first succesful request. We'll stick with
* 11 for now, as it avoids having to hard code yet more
* physical addresses into the code.
*/
psSysSpecData->psGPTimer = omap_dm_timer_request_specific(GPTIMER_TO_USE);
if (psSysSpecData->psGPTimer == NULL)
{
PVR_DPF((PVR_DBG_WARNING, "%s: omap_dm_timer_request_specific failed", __FUNCTION__));
return PVRSRV_ERROR_CLOCK_REQUEST_FAILED;
}
omap_dm_timer_set_source(psSysSpecData->psGPTimer, OMAP_TIMER_SRC_SYS_CLK);
omap_dm_timer_enable(psSysSpecData->psGPTimer);
/* Set autoreload, and start value of 0 */
omap_dm_timer_set_load_start(psSysSpecData->psGPTimer, 1, 0);
omap_dm_timer_start(psSysSpecData->psGPTimer);
/*
* The DM timer API doesn't have a mechanism for obtaining the
* physical address of the counter register.
*/
psSysSpecData->sTimerRegPhysBase.uiAddr = SYS_OMAP3430_GP11TIMER_REGS_SYS_PHYS_BASE;
#else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(3,4,0)) || !defined(MODULE) */
(void)psSysSpecData;
#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(3,4,0)) || !defined(MODULE) */
return PVRSRV_OK;
}
/*
* IOCTL commands
* TESTED
* PARAMETERS:
* cmd - 0xffc1 start, 0xffc2 stop, 0xffc3 set
* arg - value to write to timer
*/
ssize_t HRTDriver_dmtimer_ioctl(struct file *file, unsigned int cmd, unsigned int arg) {
printk("IOCTL entered\n\n");
switch(cmd) {
case 0xffc1:
printk("\nStarting the timer.\n");
omap_dm_timer_start(hrt_devp->gptimer);
return 0;
case 0xffc2:
printk("\nStopping the timer.\n\n");
omap_dm_timer_stop(hrt_devp->gptimer);
return 0;
case 0xffc3:
printk("\nSetting the timer\n\n");
omap_dm_timer_write_counter(hrt_devp->gptimer, arg);
return 0;
default:
return -1;
}
/*
//start command
if (!strcmp(cmd, "0xffc1")) {
printk("\nStarting the timer.\n");
omap_dm_timer_start(hrt_devp->gptimer);
return 0;
}
else if (!strcmp(cmd, "0xffc2")) {
printk("\nStopping the timer.\n\n");
omap_dm_timer_stop(hrt_devp->gptimer);
return 0;
}
else if (!strcmp(cmd, "0xffc3")) {
printk("\nSetting the timer\n\n");
omap_dm_timer_write_counter(hrt_devp->gptimer, arg);
return 0;
}
else return -1;
*/
}
static void omap_pwm_led_set_pwm_cycle(struct omap_pwm_led *led, int cycle)
{
int n;
if (cycle == 0)
n = 0xff;
else n = cycle - 1;
if (cycle == LED_FULL) {
omap_dm_timer_set_pwm(led->intensity_timer, 0, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_stop(led->intensity_timer);
} else {
omap_dm_timer_set_pwm(led->intensity_timer, 1, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_set_match(led->intensity_timer, 1,
(0xffffff00) | cycle);
omap_dm_timer_start(led->intensity_timer);
}
}
static inline int proc44x_wakeup(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct omap_rproc *obj = (struct omap_rproc *)platform_get_drvdata(
to_platform_device(dev));
int ret = 0;
if (obj->dmtimer)
omap_dm_timer_start(obj->dmtimer);
ret = omap_device_enable(pdev);
if (ret)
goto err_start;
obj->state = OMAP_RPROC_RUNNING;
return 0;
err_start:
dev_err(dev, "%s error 0x%x\n", __func__, ret);
return ret;
}
/*
* Request dmtimer
* TESTED
*/
struct omap_dm_timer *HRTDriver_reserve_timer(void) {
//Get device private data
//struct HRT_dev *hrt_devp = file->private_data;
struct omap_dm_timer *timer;
timer = omap_dm_timer_request();
omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK);
omap_dm_timer_enable(timer);
if (!timer) printk("\nTimer not reserved!\n");
else printk("\nTimer succesfully reserved!\n");
//setting the load enables the timer
//omap_dm_timer_set_load_start(hrt_devp->gptimer, 0, 0);
omap_dm_timer_start(timer);
return timer;
}
static int ltn101al03_power_on(struct omap_dss_device *dssdev)
{
struct ltn101al03 *lcd = dev_get_drvdata(&dssdev->dev);
int ret = 0;
pr_info("(%s): called (@%d)\n", __func__, __LINE__);
if (lcd->enabled != 1) {
if (lcd->pdata->set_power)
lcd->pdata->set_power(true);
ret = omapdss_dpi_display_enable(dssdev);
if (ret) {
dev_err(&dssdev->dev, "failed to enable DPI\n");
goto err;
}
/* reset ltn101al03 bridge */
if (!dssdev->skip_init) {
ltn101al03_hw_reset(dssdev);
msleep(100);
gpio_set_value(lcd->pdata->led_backlight_reset_gpio, 1);
mdelay(10);
omap_dm_timer_start(lcd->gptimer);
usleep_range(2000, 2100);
update_brightness(dssdev);
}
lcd->enabled = 1;
}
if (dssdev->skip_init)
dssdev->skip_init = false;
err:
return ret;
}
static int panel_set_vcom_level(
struct omap_display *disp, int level)
{
pr_debug("panel_set_vcom_level [%s] %i\n",
disp->panel->name, level);
/* clamp the level */
if (level < 0)
level = 0;
if (level > 255)
level = 255;
/* nothing to do if levels are equal */
if (vcom_level == level)
return 0;
/* stop vcom? */
if (level == 0) {
omap_dm_timer_stop(vcom_pwm);
omap_dm_timer_disable(vcom_pwm);
vcom_level = 0;
return 0;
}
/* start vcom? */
if (vcom_level == 0) {
omap_dm_timer_enable(vcom_pwm);
omap_dm_timer_set_pwm(vcom_pwm, 0, 1, 2);
omap_dm_timer_start(vcom_pwm);
}
vcom_level = level;
pwm_set_speed(vcom_pwm, 10000, vcom_level);
vcom_level = level;
return 0;
}
static inline void omap2_gp_timer_start(unsigned long load_val)
{
omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
omap_dm_timer_start(gptimer);
}
static int __init pwm_start(void) {
int ret = 0;
struct clk *timer_fclk;
uint32_t gt_rate;
printk(KERN_INFO "Loading PWM Module... \n");
// request any timer
timer_ptr = omap_dm_timer_request();
if(timer_ptr == NULL){
// no timers available
printk("pwm module: No more gp timers available, bailing out\n");
return -1;
}
// set the clock source to the system clock
ret = omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_SYS_CLK);
if(ret) {
printk("pwm module: could not set source\n");
return -1;
}
// set prescalar to 1:1
omap_dm_timer_set_prescaler(timer_ptr, 0);
// figure out what IRQ our timer triggers
timer_irq = omap_dm_timer_get_irq(timer_ptr);
// install our IRQ handler for our timer
ret = request_irq(timer_irq, timer_irq_handler, IRQF_DISABLED | IRQF_TIMER , "pwm", timer_irq_handler);
if(ret){
printk("pwm module: request_irq failed (on irq %d), bailing out\n", timer_irq);
return ret;
}
// get clock rate in Hz and add it to struct
timer_fclk = omap_dm_timer_get_fclk(timer_ptr);
gt_rate = clk_get_rate(timer_fclk);
pwm_data_ptr.timer_rate = gt_rate;
// set preload, and autoreload
// we set it to a default of 1kHz
set_pwm_freq(1000);
// setup timer to trigger IRQ on the overflow
omap_dm_timer_set_int_enable(timer_ptr, OMAP_TIMER_INT_OVERFLOW);
// start the timer
omap_dm_timer_start(timer_ptr);
// done!
printk("pwm module: GP Timer initialized and started (%lu Hz, IRQ %d)\n", (long unsigned)gt_rate, timer_irq);
// setup a GPIO
pwm_setup_pin(38);
pwm_data_ptr.pin = 38;
set_pwm_dutycycle(1,150);
// return success
return 0;
}
static void gp_irblaster_init(int carrier_frequency, int no_carrier, unsigned short *pt_cycles_list)
{
u32 val;
u32 period;
int min_cycle=0x70000000; /* this min cycle can be set to another minimum: but which value ? */
unsigned short *pt = pt_cycles_list;
irb_over = 0;
//_select_irb_config();
/* find min cycle */
while ( *pt != 0) {
if ( *pt < min_cycle )
min_cycle = *pt;
pt++;
}
/* enable timer clock */
omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_PWM].timer);
omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer);
irq_irblaster_cycles = pt_cycles_list;
if ( no_carrier ) {
/* set the callback irq function */
_callback_irblaster_timer_interrupt = omap2_irblaster_timer_interrupt_no_carrier;
/* set IRBLASTER TIMER PWM */
/* default output is 0 */
/* toogle */
/* trigger on overflow */
omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_PWM].timer,0,1,1);
/* set frequency */
period = _get_innotech_period(gpt_pwm_list[IRBLASTER_PWM].rate,carrier_frequency);
gpt_pwm_list[IRBLASTER_PWM].period = period;
/* at init, nothing to do during few cycles */
/* and let say, during min cycle */
val = 0xFFFFFFFF+1-(period*min_cycle);
omap_dm_timer_set_load(gpt_pwm_list[IRBLASTER_PWM].timer, 1, val);
/* set IRBLASTER TIMER CTRL */
/* timer freq is the same as the carrier */
period = _get_innotech_period(gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate,carrier_frequency);
gpt_pwm_list[IRBLASTER_TIMER_CTRL].period = period;
/* at init, nothing to do during few cycles */
/* and let say, during min cycle */
val = 0xFFFFFFFF+1-(period*min_cycle);
omap_dm_timer_set_load(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 1, val);
/* prepare the irblaster match condition */
/* irblaster timer run twice time faster than the pwm */
/* so this match is set on the middle of the min cycle time */
val = 0xFFFFFFFF+1-(period*min_cycle/2);
omap_dm_timer_set_match(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 1, val);
} else {
/* set the callback irq function */
_callback_irblaster_timer_interrupt = omap2_irblaster_timer_interrupt_carrier;
/* set IRBLASTER TIMER PWM */
/* default output is 0 */
/* toogle */
/* trigger on match and overflow */
omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_PWM].timer,0,1,2);
/* set waveform frequency and duty cycle 1/2 = 128/256 */
_set_innotech_speed(IRBLASTER_PWM,carrier_frequency,128);
/* at init, no trigger = default output on pin */
irq_irblaster_pwm_ctrl_reg = omap_dm_timer_read_reg(gpt_pwm_list[IRBLASTER_PWM].timer, OMAP_TIMER_CTRL_REG);
irq_irblaster_pwm_ctrl_reg &= ~(3<<10);
omap_dm_timer_write_reg(gpt_pwm_list[IRBLASTER_PWM].timer, OMAP_TIMER_CTRL_REG, irq_irblaster_pwm_ctrl_reg);
/* make the start readuy */
irq_irblaster_pwm_ctrl_reg |= OMAP_TIMER_CTRL_ST;
/* set IRBLASTER TIMER CTRL */
/* timer freq is the same as the carrier */
period = _get_innotech_period(gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate,carrier_frequency);
gpt_pwm_list[IRBLASTER_TIMER_CTRL].period = period;
/* at init, nothing to do during few cycles */
/* and let say, during min cycle */
val = 0xFFFFFFFF+1-(period*(*irq_irblaster_cycles));
omap_dm_timer_set_load(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 1, val);
/* set the irblaster ctrl timer match condition */
/* to the middle of min cycle */
/* from (end_of_cycle - min_cycle/2) to end_of_cycle, */
/* the timer ctrl irq will pool ...*/
// val = 0xFFFFFFFF+1-(period*min_cycle/2);
val = 0xFFFFFFFF+1-_get_best_match_timing_int(min_cycle,gpt_pwm_list[IRBLASTER_TIMER_CTRL].period,gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate);
omap_dm_timer_set_match(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 1,val );
}
omap_dm_timer_start(gpt_pwm_list[ IRBLASTER_TIMER_CTRL].timer);
omap_dm_timer_start(gpt_pwm_list[ IRBLASTER_PWM].timer);
}
