static irqreturn_t omap2_irblaster_timer_interrupt_no_carrier(void)
{
int next_cycle;
struct omap_dm_timer *timer_ctrl = gpt_pwm_list[ IRBLASTER_TIMER_CTRL].timer;
struct omap_dm_timer *timer_pwm = gpt_pwm_list[ IRBLASTER_PWM ].timer;
unsigned int timer_ctrl_period = gpt_pwm_list[ IRBLASTER_TIMER_CTRL].period;
unsigned int timer_pwm_period = gpt_pwm_list[ IRBLASTER_PWM].period;
omap_dm_timer_write_status(timer_ctrl, OMAP_TIMER_INT_MATCH);
_gio_debug_clear();
next_cycle = *irq_irblaster_cycles;
if ( next_cycle ) {
irq_irblaster_cycles++;
gpt_set_new_cycle(timer_ctrl,timer_ctrl_period, next_cycle);
gpt_set_new_cycle(timer_pwm,timer_pwm_period, next_cycle);
}
else {
/* no trigger */
omap_dm_timer_set_pwm(timer_pwm,0,1,0);
/* stop timers */
omap_dm_timer_stop(timer_pwm);
omap_dm_timer_stop(timer_ctrl);
irb_over = 1;
wake_up_interruptible(&irb_wait);
}
_gio_debug_set();
return IRQ_HANDLED;
}
static void omap_pwm_led_set_blink(struct omap_pwm_led *led)
{
pr_debug("%s%s: \n", PASS1,__func__);
if (!led->powered)
return;
if (led->on_period != 0 && led->off_period != 0) {
unsigned long load_reg, cmp_reg;
load_reg = 32768 * (led->on_period + led->off_period) / 1000;
cmp_reg = 32768 * led->on_period / 1000;
omap_dm_timer_stop(led->blink_timer);
omap_dm_timer_set_load(led->blink_timer, 1, -load_reg);
omap_dm_timer_set_match(led->blink_timer, 1, -cmp_reg);
omap_dm_timer_set_pwm(led->blink_timer, 1, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_write_counter(led->blink_timer, -2);
omap_dm_timer_start(led->blink_timer);
} else {
omap_dm_timer_set_pwm(led->blink_timer, 1, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_stop(led->blink_timer);
}
}
static irqreturn_t omap2_irblaster_timer_interrupt_carrier(void)
{
static int toggle=0;
static int next_cycle=0;
struct omap_dm_timer *timer_ctrl = gpt_pwm_list[ IRBLASTER_TIMER_CTRL].timer;
struct omap_dm_timer *timer_pwm = gpt_pwm_list[ IRBLASTER_PWM ].timer;
unsigned int timer_ctrl_period = gpt_pwm_list[ IRBLASTER_TIMER_CTRL].period;
const unsigned int counter_lim = 0xFFFFFFFF+1-(timer_ctrl_period/2)+1;
_gio_debug_clear();
omap_dm_timer_write_status(timer_ctrl, OMAP_TIMER_INT_MATCH);
next_cycle = *irq_irblaster_cycles;
if ( next_cycle ) {
irq_irblaster_cycles++;
gpt_set_new_cycle(timer_ctrl,timer_ctrl_period, next_cycle);
}
if (toggle) {
/* no trigger */
irq_irblaster_pwm_ctrl_reg &= ~(3<<10);
} else {
/* trigger on overflow and match */
/* output carrier */
irq_irblaster_pwm_ctrl_reg |= (2<<10);
}
toggle = (toggle+1)&0x1;
if ( !next_cycle ) {
/* stop timers */
omap_dm_timer_stop(timer_ctrl);
omap_dm_timer_stop(timer_pwm);
/* reset toogle */
toggle=0;
next_cycle=0;
irb_over = 1;
wake_up_interruptible(&irb_wait);
goto intr_end;
}
/* wait for overflow */
/* FIXME: try to find something that leaves cpu some ressources*/
while ( omap_dm_timer_read_counter(timer_ctrl) < counter_lim)
cpu_relax();
/* active/desactive pwm */
omap_dm_timer_write_reg(timer_pwm, OMAP_TIMER_CTRL_REG, irq_irblaster_pwm_ctrl_reg);
intr_end:
_gio_debug_set();
return IRQ_HANDLED;
}
static irqreturn_t lirc_rx51_interrupt_handler(int irq, void *ptr)
{
unsigned int retval;
struct lirc_rx51 *lirc_rx51 = ptr;
retval = omap_dm_timer_read_status(lirc_rx51->pulse_timer);
if (!retval)
return IRQ_NONE;
if (retval & ~OMAP_TIMER_INT_MATCH)
dev_err_ratelimited(lirc_rx51->dev,
": Unexpected interrupt source: %x\n", retval);
omap_dm_timer_write_status(lirc_rx51->pulse_timer,
OMAP_TIMER_INT_MATCH |
OMAP_TIMER_INT_OVERFLOW |
OMAP_TIMER_INT_CAPTURE);
if (lirc_rx51->wbuf_index < 0) {
dev_err_ratelimited(lirc_rx51->dev,
": BUG wbuf_index has value of %i\n",
lirc_rx51->wbuf_index);
goto end;
}
/*
* If we happen to hit an odd latency spike, loop through the
* pulses until we catch up.
*/
do {
if (lirc_rx51->wbuf_index >= WBUF_LEN)
goto end;
if (lirc_rx51->wbuf[lirc_rx51->wbuf_index] == -1)
goto end;
if (lirc_rx51->wbuf_index % 2)
lirc_rx51_off(lirc_rx51);
else
lirc_rx51_on(lirc_rx51);
retval = pulse_timer_set_timeout(lirc_rx51,
lirc_rx51->wbuf[lirc_rx51->wbuf_index]);
lirc_rx51->wbuf_index++;
} while (retval);
return IRQ_HANDLED;
end:
/* Stop TX here */
lirc_rx51_off(lirc_rx51);
lirc_rx51->wbuf_index = -1;
omap_dm_timer_stop(lirc_rx51->pwm_timer);
omap_dm_timer_stop(lirc_rx51->pulse_timer);
omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer, 0);
wake_up_interruptible(&lirc_rx51->wqueue);
return IRQ_HANDLED;
}
long hrt_ioctl(struct file* file,unsigned int cmd, unsigned long arg)
{
switch(cmd)
{
case CMD_START_TIMER:
if (!omap_dm_timer_start(timer))
{
return -EINVAL;
}
break;
case CMD_STOP_TIMER:
if (!omap_dm_timer_stop(timer))
{
return -EINVAL;
}
break;
case CMD_SET_TIMER_COUNTER_VALUE:
if(!omap_dm_timer_write_counter(timer,(int)arg))
{
return -EINVAL;
}
break;
default:
return -ENOTTY;
break;
}
return 0;
}
static void set_gptimer_pwm_vibrator(int on)
{
unsigned long flags;
if (pwm_timer == NULL) {
pr_err(KERN_ERR "vibrator pwm timer is NULL\n");
return;
}
spin_lock_irqsave(&vibe__timer_lock, flags);
if (on) {
if(!vibe_timer_state) {
gpio_set_value(GPIO_VIB_EN, 1);
omap_dm_timer_enable(pwm_timer);
omap_dm_timer_set_match(pwm_timer, 1, 0xFFFFFFFE);
omap_dm_timer_set_pwm(pwm_timer, 0, 1, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_set_load_start(pwm_timer, 1, MOTOR_RESONANCE_COUTER_VALUE);
vibe_timer_state = 1;
}
} else {
if(vibe_timer_state) {
omap_dm_timer_stop(pwm_timer);
omap_dm_timer_disable(pwm_timer);
gpio_set_value(GPIO_VIB_EN, 0);
vibe_timer_state = 0;
}
}
spin_unlock_irqrestore(&vibe__timer_lock, flags);
}
static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
u32 period;
omap_dm_timer_stop(gptimer);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
period -= 1;
omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
case CLOCK_EVT_MODE_SHUTDOWN:
omap_timer_save_context(gptimer);
break;
case CLOCK_EVT_MODE_RESUME:
omap_timer_restore_context(gptimer);
break;
case CLOCK_EVT_MODE_UNUSED:
break;
}
}
int omap_rproc_activate(struct omap_device *od)
{
int i, ret = 0;
struct rproc *rproc = platform_get_drvdata(&od->pdev);
struct device *dev = rproc->dev;
struct omap_rproc_pdata *pdata = dev->platform_data;
struct omap_rproc_timers_info *timers = pdata->timers;
struct omap_rproc_priv *rpp = rproc->priv;
#ifdef CONFIG_REMOTE_PROC_AUTOSUSPEND
struct iommu *iommu;
if (!rpp->iommu) {
iommu = iommu_get(pdata->iommu_name);
if (IS_ERR(iommu)) {
dev_err(dev, "iommu_get error: %ld\n",
PTR_ERR(iommu));
return PTR_ERR(iommu);
}
rpp->iommu = iommu;
}
if (!rpp->mbox)
rpp->mbox = omap_mbox_get(pdata->sus_mbox_name, NULL);
#endif
/**
* explicitly configure a boot address from which remoteproc
* starts executing code when taken out of reset.
*/
_load_boot_addr(rproc, rpp->bootaddr);
/**
* Domain is in HW SUP thus in hw_auto but
* since remoteproc will be enabled clkdm
* needs to be in sw_sup (Do not let it idle).
*/
if (pdata->clkdm)
clkdm_wakeup(pdata->clkdm);
for (i = 0; i < pdata->timers_cnt; i++)
omap_dm_timer_start(timers[i].odt);
for (i = 0; i < od->hwmods_cnt; i++) {
ret = omap_hwmod_enable(od->hwmods[i]);
if (ret) {
for (i = 0; i < pdata->timers_cnt; i++)
omap_dm_timer_stop(timers[i].odt);
break;
}
}
/**
* Domain is in force_wkup but since remoteproc
* was enabled it is safe now to switch clkdm
* to hw_auto (let it idle).
*/
if (pdata->clkdm)
clkdm_allow_idle(pdata->clkdm);
return ret;
}
static int __devinit cloudsurfer_wakeup_probe(struct platform_device *pdev)
{
struct cloudsurfer_wakeup_struct *wkup;
struct input_dev *wkup_in;
u32 tick_rate, cycles;
int err;
/* Data structure allocation */
wkup = kzalloc(sizeof(struct cloudsurfer_wakeup_struct), GFP_KERNEL);
wkup_in = input_allocate_device();
if (!wkup_in) {
printk("CLOUDSURFER - Can't allocate wakeup timer input\n");
err = -ENOMEM;
goto error_input_dev;
}
/* Timer allocation and setup */
if ( (wkup->timer=omap_dm_timer_request_specific(1)) == NULL ) {
printk("CLOUDSURFER - can't allocate wakeup timer\n");
err = -ENODEV;
goto error_timer;
}
wkup->irq = omap_dm_timer_get_irq(wkup->timer);
omap_dm_timer_set_source(wkup->timer,OMAP_TIMER_SRC_32_KHZ);
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(wkup->timer));
cycles = tick_rate * wakeup_seconds;
omap_dm_timer_stop(wkup->timer);
input_set_capability(wkup_in,EV_MSC,1);
input_set_capability(wkup_in,EV_MSC,2);
wkup_in->name = "cloudsurfer-wakeup";
wkup_in->phys = "cloudsurfer-wakeup/input0";
wkup_in->dev.parent = &pdev->dev;
cloudsurfer_irq_data.dev_id = wkup_in;
setup_irq(wkup->irq,&cloudsurfer_irq_data);
input_set_drvdata(wkup_in, wkup);
err = input_register_device(wkup_in);
if (err) {
printk("CLOUDSURFER -Can't register wakeup timer: %d\n", err);
goto error_register;
}
omap_dm_timer_set_int_enable(wkup->timer,OMAP_TIMER_INT_OVERFLOW);
omap_dm_timer_set_load_start(wkup->timer, 1, 0xffffffff - cycles);
platform_set_drvdata(pdev, wkup_in);
return 0;
error_register:
free_irq(wkup->irq, NULL);
error_timer:
input_free_device(wkup_in);
error_input_dev:
kfree(wkup);
return err;
}
static ssize_t store_irblaster_freq(struct device *dev, struct device_attribute *attr,
const char* buf, size_t len)
{
frequency = simple_strtol(buf, NULL, 10);
/* Disable pwm */
if (frequency == 0) {
omap_dm_timer_stop(irb_pwm_timer);
omap_dm_timer_disable(irb_pwm_timer);
irb_state = 0;
return 0;
}
/* Enable pwm */
if (irb_state == 0) {
omap_dm_timer_enable(irb_pwm_timer);
omap_dm_timer_set_pwm(irb_pwm_timer, 0, 1, 2);
omap_dm_timer_start(irb_pwm_timer);
irb_state = 1;
}
pwm_set_speed(irb_pwm_timer, frequency, duty_cycle);
return len;
}
static void omap_pwm_led_set_pwm_cycle(struct omap_pwm_led *led, int cycle)
{
int pwm_frequency = 10000;
int def_on;
pr_debug("%s: cycle: %i\n",
__func__, cycle);
if (led->pdata->bkl_max)
cycle = ( (cycle * led->pdata->bkl_max ) / 255);
if (cycle < led->pdata->bkl_min)
cycle = led->pdata->bkl_min;
if (led->pdata->bkl_freq)
pwm_frequency = led->pdata->bkl_freq;
if (cycle != LED_FULL)
def_on = led->pdata->invert ? 1:0;
else
def_on = led->pdata->invert ? 0:1;
omap_dm_timer_set_pwm(led->intensity_timer, def_on, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
if (cycle != LED_FULL) {
pwm_set_speed(led->intensity_timer, pwm_frequency, 256-cycle);
omap_dm_timer_start(led->intensity_timer);
} else
omap_dm_timer_stop(led->intensity_timer);
}
static void sholest_lvibrator_power_off(void)
{
#ifdef CONFIG_VIB_PWM
gpio_set_value(SHOLEST_VIBRATOR_EN_GPIO, 0);
#endif
omap_dm_timer_stop(vib_pwm_timer);
omap_dm_timer_disable(vib_pwm_timer);
}
static void backlight_gptimer_stop(struct omap_dss_device *dssdev)
{
struct ltn101al03 *lcd = dev_get_drvdata(&dssdev->dev);
int ret;
ret = omap_dm_timer_stop(lcd->gptimer);
if (ret)
pr_err("failed to stop pwm timer. ret=%d\n", ret);
}
static void omap_pwm_led_power_off(struct omap_pwm_led *led)
{
if (!led->powered)
return;
led->powered = 0;
pr_debug("%s: brightness: %i\n",
__func__, led->brightness);
if (led->pdata->set_power != NULL)
led->pdata->set_power(led->pdata, 0);
/* Everything off */
omap_dm_timer_stop(led->intensity_timer);
if (led->blink_timer != NULL)
omap_dm_timer_stop(led->blink_timer);
}
static void omap_pwm_led_power_off(struct omap_pwm_led *led)
{
if (!led->powered)
return;
led->powered = 0;
/* Everything off */
omap_dm_timer_stop(led->intensity_timer);
omap_dm_timer_disable(led->intensity_timer);
if (led->blink_timer != NULL) {
omap_dm_timer_stop(led->blink_timer);
omap_dm_timer_disable(led->blink_timer);
}
if (led->pdata->set_power != NULL)
led->pdata->set_power(led->pdata, 0);
}
int finish_gptimer12 ( void )
{
omap_dm_timer_stop( battery_timer );
omap_dm_timer_write_status( battery_timer, OMAP_TIMER_INT_OVERFLOW );
omap_dm_timer_set_int_enable( battery_timer, 0 );
return 0;
}
static void __exit gptimer_request_exit(void)
{
/*Stop the timer*/
omap_dm_timer_stop(timer_ptr);
/*Release the timer*/
omap_dm_timer_free(timer_ptr);
printk(KERN_INFO "GP Timer finalized and stoped\n");
}
// Cleanup after ourselfs
static void __exit gptimer_test_exit(void)
{
printk("gptimer test: cleanup called\n");
// stop the timer
omap_dm_timer_stop(timer_ptr);
// release the IRQ handler
free_irq(timer_irq, timer_irq_handler);
// release the timer
omap_dm_timer_free(timer_ptr);
}
void pwm_gpt_stop(int id)
{
if ( !_check_id(id) ) {
return;
}
if ( !_check_timer(id) ) {
return;
}
omap_dm_timer_stop(gpt_pwm_list[id].timer);
omap_dm_timer_disable(gpt_pwm_list[id].timer);
}
static void omap_pwm_led_power_off(struct omap_pwm_led *led)
{
pr_debug("%s%s: \n", PASS1,__func__);
printk("!!!!!!!!!!%s the brightness is %d \n",__func__, led->brightness);
if (!led->powered)
return;
led->powered = 0;
/* Everything off */
omap_dm_timer_set_pwm(led->intensity_timer, 0, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_stop(led->intensity_timer);
omap_dm_timer_disable(led->intensity_timer);
if (led->blink_timer != NULL) {
omap_dm_timer_stop(led->blink_timer);
omap_dm_timer_disable(led->blink_timer);
}
if (led->pdata->set_power != NULL)
led->pdata->set_power(led->pdata, 0);
}
static int panel_set_backlight_level(
struct omap_display *disp, int level)
{
int hw_level;
pr_debug("panel_set_backlight_level [%s] %d\n",
disp != NULL ? disp->panel->name: "cpt_wvga_48", level);
/* skip if panel is not on */
if (panel_state == 0) {
saved_bkl_level = level;
return 0;
}
/* clamp the level */
if (level < 0)
level = 0;
if (level > 255)
level = 255;
/* nothing to do if levels are equal */
if (bkl_level == level)
return 0;
/* stop backlight? */
if (level == 0) {
if (GPIO_EXISTS(display_gpio.bkl_pwon))
omap_set_gpio_dataout(GPIO_PIN(display_gpio.bkl_pwon), 0);
omap_dm_timer_stop(bkl_pwm);
omap_dm_timer_disable(bkl_pwm);
bkl_level = 0;
return 0;
}
/* start backlight? */
if (bkl_level == 0) {
omap_dm_timer_enable(bkl_pwm);
omap_dm_timer_set_pwm(bkl_pwm, 0, 1, 2);
omap_dm_timer_start(bkl_pwm);
if (GPIO_EXISTS(display_gpio.bkl_pwon))
omap_set_gpio_dataout(GPIO_PIN(display_gpio.bkl_pwon), 1);
}
/* set new level, g7 machines have inverted level */
hw_level = level;
if (!machine_is_archos_g6h())
hw_level = 255 - level;
pwm_set_speed(bkl_pwm, 10000, hw_level);
bkl_level = level;
return 0;
}
static void __exit pwm_end(void) {
printk(KERN_INFO "Exiting PWM Module. \n");
// stop the timer
omap_dm_timer_stop(timer_ptr);
// release the IRQ handler
free_irq(timer_irq, timer_irq_handler);
// release the timer
omap_dm_timer_free(timer_ptr);
// release GPIO
gpio_free(pwm_data_ptr.pin);
}
/*!
******************************************************************************
@Function ReleaseGPTimer
@Description Release a GP timer
@Return PVRSRV_ERROR
******************************************************************************/
static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
if (psSysSpecData->psGPTimer != NULL)
{
/* Always returns 0 */
(void) omap_dm_timer_stop(psSysSpecData->psGPTimer);
omap_dm_timer_disable(psSysSpecData->psGPTimer);
omap_dm_timer_free(psSysSpecData->psGPTimer);
psSysSpecData->sTimerRegPhysBase.uiAddr = 0;
psSysSpecData->psGPTimer = NULL;
}
}
/*!
******************************************************************************
@Function ReleaseGPTimer
@Description Release a GP timer
@Return PVRSRV_ERROR
******************************************************************************/
static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
if (psSysSpecData->psGPTimer != NULL)
{
/* Always returns 0 */
(void) omap_dm_timer_stop(psSysSpecData->psGPTimer);
omap_dm_timer_disable(psSysSpecData->psGPTimer);
omap_dm_timer_free(psSysSpecData->psGPTimer);
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
psSysSpecData->sTimerRegPhysBase.uiAddr = 0;
#endif
psSysSpecData->psGPTimer = NULL;
}
}
static inline int proc44x_sleep(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct omap_rproc *obj = (struct omap_rproc *)platform_get_drvdata(
to_platform_device(dev));
int ret = 0;
if (obj->state == OMAP_RPROC_RUNNING) {
ret = omap_device_shutdown(pdev);
if (ret)
dev_err(dev, "%s err 0x%x\n", __func__, ret);
if (obj->dmtimer)
omap_dm_timer_stop(obj->dmtimer);
}
obj->state = OMAP_RPROC_HIBERNATING;
return ret;
}
/*
* IOCTL commands
* TESTED
* PARAMETERS:
* cmd - 0xffc1 start, 0xffc2 stop, 0xffc3 set
* arg - value to write to timer
*/
ssize_t HRTDriver_dmtimer_ioctl(struct file *file, unsigned int cmd, unsigned int arg) {
printk("IOCTL entered\n\n");
switch(cmd) {
case 0xffc1:
printk("\nStarting the timer.\n");
omap_dm_timer_start(hrt_devp->gptimer);
return 0;
case 0xffc2:
printk("\nStopping the timer.\n\n");
omap_dm_timer_stop(hrt_devp->gptimer);
return 0;
case 0xffc3:
printk("\nSetting the timer\n\n");
omap_dm_timer_write_counter(hrt_devp->gptimer, arg);
return 0;
default:
return -1;
}
/*
//start command
if (!strcmp(cmd, "0xffc1")) {
printk("\nStarting the timer.\n");
omap_dm_timer_start(hrt_devp->gptimer);
return 0;
}
else if (!strcmp(cmd, "0xffc2")) {
printk("\nStopping the timer.\n\n");
omap_dm_timer_stop(hrt_devp->gptimer);
return 0;
}
else if (!strcmp(cmd, "0xffc3")) {
printk("\nSetting the timer\n\n");
omap_dm_timer_write_counter(hrt_devp->gptimer, arg);
return 0;
}
else return -1;
*/
}
static void omap_pwm_led_set_pwm_cycle(struct omap_pwm_led *led, int cycle)
{
int n;
if (cycle == 0)
n = 0xff;
else n = cycle - 1;
if (cycle == LED_FULL) {
omap_dm_timer_set_pwm(led->intensity_timer, 0, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_stop(led->intensity_timer);
} else {
omap_dm_timer_set_pwm(led->intensity_timer, 1, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_set_match(led->intensity_timer, 1,
(0xffffff00) | cycle);
omap_dm_timer_start(led->intensity_timer);
}
}
int omap_rproc_deactivate(struct omap_device *od)
{
int i, ret = 0;
struct rproc *rproc = platform_get_drvdata(&od->pdev);
struct device *dev = rproc->dev;
struct omap_rproc_pdata *pdata = dev->platform_data;
struct omap_rproc_timers_info *timers = pdata->timers;
#ifdef CONFIG_REMOTE_PROC_AUTOSUSPEND
struct omap_rproc_priv *rpp = rproc->priv;
#endif
if (pdata->clkdm)
clkdm_wakeup(pdata->clkdm);
for (i = 0; i < od->hwmods_cnt; i++) {
ret = omap_hwmod_shutdown(od->hwmods[i]);
if (ret)
goto err;
}
for (i = 0; i < pdata->timers_cnt; i++)
omap_dm_timer_stop(timers[i].odt);
#ifdef CONFIG_REMOTE_PROC_AUTOSUSPEND
if (rpp->iommu) {
iommu_put(rpp->iommu);
rpp->iommu = NULL;
}
if (rpp->mbox) {
omap_mbox_put(rpp->mbox, NULL);
rpp->mbox = NULL;
}
#endif
err:
if (pdata->clkdm)
clkdm_allow_idle(pdata->clkdm);
return ret;
}
static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
u32 period;
omap_dm_timer_stop(gptimer);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
period -= 1;
if (cpu_is_omap44xx())
period = 0xff; /* FIXME: */
omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static int panel_set_vcom_level(
struct omap_display *disp, int level)
{
pr_debug("panel_set_vcom_level [%s] %i\n",
disp->panel->name, level);
/* clamp the level */
if (level < 0)
level = 0;
if (level > 255)
level = 255;
/* nothing to do if levels are equal */
if (vcom_level == level)
return 0;
/* stop vcom? */
if (level == 0) {
omap_dm_timer_stop(vcom_pwm);
omap_dm_timer_disable(vcom_pwm);
vcom_level = 0;
return 0;
}
/* start vcom? */
if (vcom_level == 0) {
omap_dm_timer_enable(vcom_pwm);
omap_dm_timer_set_pwm(vcom_pwm, 0, 1, 2);
omap_dm_timer_start(vcom_pwm);
}
vcom_level = level;
pwm_set_speed(vcom_pwm, 10000, vcom_level);
vcom_level = level;
return 0;
}