/* * --------------------------------------------------------------------------- * Timer initialization * --------------------------------------------------------------------------- */ int __init omap_32k_timer_init(void) { int ret = -ENODEV; if (cpu_is_omap16xx()) { void __iomem *base; struct clk *sync32k_ick; base = ioremap(OMAP1_32KSYNC_TIMER_BASE, SZ_1K); if (!base) { pr_err("32k_counter: failed to map base addr\n"); return -ENODEV; } sync32k_ick = clk_get(NULL, "omap_32ksync_ick"); if (!IS_ERR(sync32k_ick)) clk_enable(sync32k_ick); ret = omap_init_clocksource_32k(base); } if (!ret) omap_init_32k_timer(); return ret; }
/* * --------------------------------------------------------------------------- * Timer initialization * --------------------------------------------------------------------------- */ bool __init omap_32k_timer_init(void) { omap_init_clocksource_32k(); omap_init_32k_timer(); return true; }
/* Setup free-running counter for clocksource */ static int __init __maybe_unused omap2_sync32k_clocksource_init(void) { int ret; struct device_node *np = NULL; struct omap_hwmod *oh; void __iomem *vbase; const char *oh_name = "counter_32k"; /* * If device-tree is present, then search the DT blob * to see if the 32kHz counter is supported. */ if (of_have_populated_dt()) { np = omap_get_timer_dt(omap_counter_match, NULL); if (!np) return -ENODEV; of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); if (!oh_name) return -ENODEV; } /* * First check hwmod data is available for sync32k counter */ oh = omap_hwmod_lookup(oh_name); if (!oh || oh->slaves_cnt == 0) return -ENODEV; omap_hwmod_setup_one(oh_name); if (np) { vbase = of_iomap(np, 0); of_node_put(np); } else { vbase = omap_hwmod_get_mpu_rt_va(oh); } if (!vbase) { pr_warn("%s: failed to get counter_32k resource\n", __func__); return -ENXIO; } ret = omap_hwmod_enable(oh); if (ret) { pr_warn("%s: failed to enable counter_32k module (%d)\n", __func__, ret); return ret; } ret = omap_init_clocksource_32k(vbase); if (ret) { pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", __func__, ret); omap_hwmod_idle(oh); } return ret; }
/* Setup free-running counter for clocksource */ static int __init omap2_sync32k_clocksource_init(void) { int ret; struct omap_hwmod *oh; void __iomem *vbase; const char *oh_name = "counter_32k"; /* * First check hwmod data is available for sync32k counter */ oh = omap_hwmod_lookup(oh_name); if (!oh || oh->slaves_cnt == 0) return -ENODEV; omap_hwmod_setup_one(oh_name); vbase = omap_hwmod_get_mpu_rt_va(oh); if (!vbase) { pr_warn("%s: failed to get counter_32k resource\n", __func__); return -ENXIO; } ret = omap_hwmod_enable(oh); if (ret) { pr_warn("%s: failed to enable counter_32k module (%d)\n", __func__, ret); return ret; } ret = omap_init_clocksource_32k(vbase); if (ret) { pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", __func__, ret); omap_hwmod_idle(oh); } return ret; }
static void __init omap2_gp_clocksource_init(void) { omap_init_clocksource_32k(); }
clockevent_32k_timer.shift); clockevent_32k_timer.max_delta_ns = clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer); clockevent_32k_timer.min_delta_ns = clockevent_delta2ns(1, &clockevent_32k_timer); clockevent_32k_timer.cpumask = cpumask_of(0); clockevents_register_device(&clockevent_32k_timer); } /* * --------------------------------------------------------------------------- * Timer initialization * --------------------------------------------------------------------------- */ bool __init omap_32k_timer_init(void) { omap_init_clocksource_32k(); omap_init_32k_timer(); return true; } et = omap_init_clocksource_32k(base); } if (!ret) omap_init_32k_timer(); return ret; }