static int __init omap_l2_cache_init(void)
{
u32 aux_ctrl = 0;
/*
* To avoid code running on other OMAPs in
* multi-omap builds
*/
if (!cpu_is_omap44xx())
return -ENODEV;
/* Static mapping, never released */
l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
BUG_ON(!l2cache_base);
/*
* 16-way associativity, parity disabled
* Way size - 32KB (es1.0)
* Way size - 64KB (es2.0 +)
*/
aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
(0x1 << 25) |
(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
if (omap_rev() == OMAP4430_REV_ES1_0) {
aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
} else {
aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
}
if (omap_rev() != OMAP4430_REV_ES1_0)
omap_smc1(0x109, aux_ctrl);
/* Enable PL310 L2 Cache controller */
omap_smc1(0x102, 0x1);
l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
/*
* Override default outer_cache.disable with a OMAP4
* specific one
*/
outer_cache.disable = omap4_l2x0_disable;
outer_cache.set_debug = omap4_l2x0_set_debug;
return 0;
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
u32 diag0_errata_flags = 0;
/* Enable NS access to SMP bit for this CPU on HS devices */
if (cpu_is_omap446x() || cpu_is_omap443x()) {
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
omap4_secure_dispatcher(PPA_SERVICE_DEFAULT_POR_NS_SMP,
FLAG_START_CRITICAL,
0, 0, 0, 0, 0);
else {
diag0_errata_flags =
omap4_get_diagctrl0_errata_flags();
if (diag0_errata_flags)
omap_smc1(HAL_DIAGREG_0, diag0_errata_flags);
}
}
/*
* If any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_secondary_init(0);
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
static void debug_writel(unsigned long val)
{
extern void omap_smc1(u32 fn, u32 arg);
/*
* Texas Instrument secure monitor api to modify the
* PL310 Debug Control Register.
*/
omap_smc1(0x100, val);
}
static int __init omap_l2_cache_init(void)
{
/*
* To avoid code running on other OMAPs in
* multi-omap builds
*/
if (!cpu_is_omap44xx())
return -ENODEV;
/* Static mapping, never released */
l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
BUG_ON(!l2cache_base);
if (omap_rev() != OMAP4430_REV_ES1_0) {
/* Set POR through PPA service only in EMU/HS devices */
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
omap4_secure_dispatcher(
PPA_SERVICE_PL310_POR, 0x7, 1,
PL310_POR, 0, 0, 0);
else
omap_smc1(0x113, 0x7);
omap_smc1(0x109, OMAP4_L2X0_AUXCTL_VALUE);
}
/* Enable PL310 L2 Cache controller */
omap_smc1(0x102, 0x1);
/*
* 32KB way size, 16-way associativity,
* parity disabled
*/
if (omap_rev() == OMAP4430_REV_ES1_0)
l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
else
l2x0_init(l2cache_base, OMAP4_L2X0_AUXCTL_VALUE, 0xd0000fff);
return 0;
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
trace_hardirqs_off();
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
/* Enable NS access to SMP bit */
omap4_secure_dispatcher(PPA_SERVICE_NS_SMP, 4, 0, 0, 0, 0, 0);
else
omap_smc1(0x114, 0x810);
/*
* If any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(0, gic_cpu_base_addr);
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
static int __init omap_l2_cache_init(void)
{
u32 aux_ctrl = 0;
u32 por_ctrl = 0;
u32 lockdown = 0;
bool mpu_prefetch_disable_errata = false;
/*
* To avoid code running on other OMAPs in
* multi-omap builds
*/
if (!cpu_is_omap44xx())
return -ENODEV;
#ifdef CONFIG_OMAP_ALLOW_OSWR
if (omap_rev() == OMAP4460_REV_ES1_0)
mpu_prefetch_disable_errata = true;
#endif
/* Static mapping, never released */
l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
if (WARN_ON(!l2cache_base))
return -ENODEV;
/*
* 16-way associativity, parity disabled
* Way size - 32KB (es1.0)
* Way size - 64KB (es2.0 +)
*/
aux_ctrl = readl_relaxed(l2cache_base + L2X0_AUX_CTRL);
if (omap_rev() == OMAP4430_REV_ES1_0) {
aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
goto skip_aux_por_api;
}
/*
* Drop instruction prefetch hint since it degrades the
* the performance.
*/
aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
if (!mpu_prefetch_disable_errata)
aux_ctrl |= (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT);
omap_smc1(0x109, aux_ctrl);
/* Setup POR Control register */
por_ctrl = readl_relaxed(l2cache_base + L2X0_PREFETCH_CTRL);
/*
* Double linefill is available only on OMAP4460 L2X0.
* It may cause single cache line memory corruption, leave it disabled
* on all devices
*/
por_ctrl &= ~(1 << L2X0_PREFETCH_DOUBLE_LINEFILL_SHIFT);
if (!mpu_prefetch_disable_errata) {
por_ctrl &= ~L2X0_POR_OFFSET_MASK;
por_ctrl |= L2X0_POR_OFFSET_VALUE;
}
/* Set POR through PPA service only in EMU/HS devices */
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
omap4_secure_dispatcher(PPA_SERVICE_PL310_POR, 0x7, 1,
por_ctrl, 0, 0, 0);
else if (omap_rev() >= OMAP4430_REV_ES2_1)
omap_smc1(0x113, por_ctrl);
/*
* FIXME: Temporary WA for OMAP4460 stability issue.
* Lock-down specific L2 cache ways which makes effective
* L2 size as 512 KB instead of 1 MB
*/
if (omap_rev() == OMAP4460_REV_ES1_0) {
lockdown = 0xa5a5;
writel_relaxed(lockdown, l2cache_base + L2X0_LOCKDOWN_WAY_D0);
writel_relaxed(lockdown, l2cache_base + L2X0_LOCKDOWN_WAY_D1);
writel_relaxed(lockdown, l2cache_base + L2X0_LOCKDOWN_WAY_I0);
writel_relaxed(lockdown, l2cache_base + L2X0_LOCKDOWN_WAY_I1);
}
skip_aux_por_api:
/* Enable PL310 L2 Cache controller */
omap_smc1(0x102, 0x1);
l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
/*
* Override default outer_cache.disable with a OMAP4
* specific one
*/
outer_cache.disable = omap4_l2x0_disable;
outer_cache.set_debug = omap4_l2x0_set_debug;
return 0;
}
static void omap4_l2x0_set_debug(unsigned long val)
{
/* Program PL310 L2 Cache controller debug register */
omap_smc1(0x100, val);
}
static void omap4_l2x0_disable(void)
{
/* Disable PL310 L2 Cache controller */
omap_smc1(0x102, 0x0);
}
void set_cntfreq(void)
{
omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
}
/*
* The realtime counter also called master counter, is a free-running
* counter, which is related to real time. It produces the count used
* by the CPU local timer peripherals in the MPU cluster. The timer counts
* at a rate of 6.144 MHz. Because the device operates on different clocks
* in different power modes, the master counter shifts operation between
* clocks, adjusting the increment per clock in hardware accordingly to
* maintain a constant count rate.
*/
static void __init realtime_counter_init(void)
{
void __iomem *base;
static struct clk *sys_clk;
unsigned long rate;
unsigned int reg, num, den;
base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
if (!base) {
pr_err("%s: ioremap failed\n", __func__);
return;
}
sys_clk = clk_get(NULL, "sys_clkin");
if (IS_ERR(sys_clk)) {
pr_err("%s: failed to get system clock handle\n", __func__);
iounmap(base);
return;
}
rate = clk_get_rate(sys_clk);
/* Numerator/denumerator values refer TRM Realtime Counter section */
switch (rate) {
case 1200000:
num = 64;
den = 125;
break;
case 1300000:
num = 768;
den = 1625;
break;
case 19200000:
num = 8;
den = 25;
break;
case 20000000:
num = 192;
den = 625;
break;
case 2600000:
num = 384;
den = 1625;
break;
case 2700000:
num = 256;
den = 1125;
break;
case 38400000:
default:
/* Program it for 38.4 MHz */
num = 4;
den = 25;
break;
}
/* Program numerator and denumerator registers */
reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
NUMERATOR_DENUMERATOR_MASK;
reg |= num;
__raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
NUMERATOR_DENUMERATOR_MASK;
reg |= den;
__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
arch_timer_freq = (rate / den) * num;
omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
iounmap(base);
}
void v7_outer_cache_disable(void)
{
omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
}
static int __init omap_l2_cache_init(void)
{
u32 l2x0_auxctrl;
u32 l2x0_por;
u32 l2x0_lockdown;
/*
* To avoid code running on other OMAPs in
* multi-omap builds
*/
if (!cpu_is_omap44xx())
return -ENODEV;
/* Static mapping, never released */
l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
BUG_ON(!l2cache_base);
if (omap_rev() == OMAP4430_REV_ES1_0) {
l2x0_auxctrl = OMAP443X_L2X0_AUXCTL_VALUE_ES1;
goto skip_auxctlr;
}
if (cpu_is_omap446x()) {
if (omap_rev() == OMAP4460_REV_ES1_0) {
l2x0_auxctrl = OMAP446X_L2X0_AUXCTL_VALUE_ES1;
l2x0_por = OMAP446X_PL310_POR_ES1;
l2x0_lockdown = 0xa5a5;
} else {
l2x0_auxctrl = OMAP446X_L2X0_AUXCTL_VALUE;
l2x0_por = OMAP446X_PL310_POR;
l2x0_lockdown = 0;
}
} else {
l2x0_auxctrl = OMAP443X_L2X0_AUXCTL_VALUE;
l2x0_por = OMAP443X_PL310_POR;
l2x0_lockdown = 0;
}
/* Set POR through PPA service only in EMU/HS devices */
if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
omap4_secure_dispatcher(
PPA_SERVICE_PL310_POR, 0x7, 1,
l2x0_por, 0, 0, 0);
} else if (omap_rev() > OMAP4430_REV_ES2_1)
omap_smc1(0x113, l2x0_por);
/*
* FIXME : Temporary WA for the OMAP4460 stability
* issue. For OMAP4460 the effective L2X0 Size = 512 KB
* with this WA.
*/
writel_relaxed(l2x0_lockdown, l2cache_base + 0x900);
writel_relaxed(l2x0_lockdown, l2cache_base + 0x908);
writel_relaxed(l2x0_lockdown, l2cache_base + 0x904);
writel_relaxed(l2x0_lockdown, l2cache_base + 0x90C);
/*
* Doble Linefill, BRESP enabled, $I and $D prefetch ON,
* Share-override = 1, NS lockdown enabled
*/
omap_smc1(0x109, l2x0_auxctrl);
skip_auxctlr:
/* Enable PL310 L2 Cache controller */
omap_smc1(0x102, 0x1);
/*
* 32KB way size, 16-way associativity,
* parity disabled
*/
l2x0_init(l2cache_base, l2x0_auxctrl, 0xd0000fff);
return 0;
}
