static int omap_defterm_putc(u8 ch)
{
if (!omap_uart_lowlevel_can_putc(omap_defterm_base, 2)) {
return VMM_EFAIL;
}
omap_uart_lowlevel_putc(omap_defterm_base, 2, ch);
return VMM_OK;
}
static u32 omap_uart_tx(struct serial *p, u8 *src, size_t len)
{
u32 i;
struct omap_uart_port *port = serial_tx_priv(p);
for (i = 0; i < len; i++) {
if (!omap_uart_lowlevel_can_putc(port->base, port->reg_shift)) {
break;
}
omap_uart_lowlevel_putc(port->base, port->reg_shift, src[i]);
}
return i;
}
static u32 omap_uart_write(struct vmm_chardev *cdev,
u8 *src, u32 len, bool sleep)
{
u32 i;
struct omap_uart_port *port;
if (!(cdev && src && cdev->priv)) {
return 0;
}
port = cdev->priv;
#if defined(OMAP_UART_USE_TXINTR)
if (sleep) {
for (i = 0; i < len; i++) {
omap_uart_putc_sleepable(port, src[i]);
}
} else {
for (i = 0; i < len; i++) {
if (!omap_uart_lowlevel_can_putc(port->base, port->reg_align)) {
break;
}
omap_uart_lowlevel_putc(port->base, port->reg_align, src[i]);
}
}
#else
for (i = 0; i < len; i++) {
if (!omap_uart_lowlevel_can_putc(port->base, port->reg_align)) {
break;
}
omap_uart_lowlevel_putc(port->base, port->reg_align, src[i]);
}
#endif
return i;
}
static void omap_uart_putc_sleepable(struct omap_uart_port *port, u8 ch)
{
/* Wait until there is space in the FIFO */
if (!omap_uart_lowlevel_can_putc(port->base, port->reg_align)) {
/* Enable the TX interrupt */
port->ier |= UART_IER_THRI;
omap_serial_out(port, UART_IER, port->ier);
/* Wait for completion */
vmm_completion_wait(&port->write_possible);
}
/* Write data to FIFO */
omap_serial_out(port, UART_THR, ch);
}
void omap_uart_lowlevel_putc(virtual_addr_t base, u32 reg_align, u8 ch)
{
while (!omap_uart_lowlevel_can_putc(base, reg_align));
omap_serial_out(UART_THR, ch);
}
