/* * Interrupt setup and service. * Have MPIC on HAWK and cascaded 8259s on Winbond cascaded to MPIC. */ static void __init mvme5100_init_IRQ(void) { #ifdef CONFIG_MVME5100_IPMC761_PRESENT int i; #endif if ( ppc_md.progress ) ppc_md.progress("init_irq: enter", 0); openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000); #ifdef CONFIG_MVME5100_IPMC761_PRESENT openpic_init(NUM_8259_INTERRUPTS); openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade", &i8259_irq); /* Map i8259 interrupts. */ for (i = 0; i < NUM_8259_INTERRUPTS; i++) irq_desc[i].handler = &i8259_pic; i8259_init(0); #else openpic_init(0); #endif if ( ppc_md.progress ) ppc_md.progress("init_irq: exit", 0); return; }
void __init tqm85xx_init_IRQ(void) { bd_t *binfo = (bd_t *) __res; /* Determine the Physical Address of the OpenPIC regs */ phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET; OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE); OpenPIC_InitSenses = tqm85xx_openpic_initsenses; OpenPIC_NumInitSenses = sizeof (tqm85xx_openpic_initsenses); /* Skip reserved space and internal sources */ openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); /* Map PIC IRQs 0-11 */ openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000); /* we let openpic interrupts starting from an offset, to * leave space for cascading interrupts underneath. */ openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET); #ifdef CONFIG_MPC8560 /* Setup CPM2 PIC */ cpm2_init_IRQ(); setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction); #endif /* CONFIG_MPC8560 */ return; }
static void __init pplus_init_IRQ(void) { int i; if (OpenPIC_Addr != NULL) openpic_init(1, NUM_8259_INTERRUPTS, 0, -1); for ( i = 0 ; i < NUM_8259_INTERRUPTS ; i++ ) irq_desc[i].handler = &i8259_pic; i8259_init(NULL); }
/* * This code assumes the exceptions management setup has already * been done. We just need to replace the exceptions that will * be handled like interrupt. On mcp750/mpc750 and many PPC processors * this means the decrementer exception and the external exception. */ void BSP_rtems_irq_mng_init(unsigned cpuId) { int i; /* * First initialize the Interrupt management hardware */ #ifdef TRACE_IRQ_INIT printk("Going to initialize openpic compliant device\n"); #endif /* FIXME (t.s.): we should probably setup the EOI delay by * passing a non-zero 'epic_freq' argument (frequency of the * EPIC serial interface) but I don't know the value on this * board (8245 SDRAM freq, IIRC)... */ openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 16, 0 /* epic_freq */); #ifdef TRACE_IRQ_INIT printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n"); #endif /* * Initialize Rtems management interrupt table */ /* * re-init the rtemsIrq table */ for (i = 0; i < BSP_IRQ_NUMBER; i++) { rtemsIrq[i] = defaultIrq; rtemsIrq[i].name = i; } /* * Init initial Interrupt management config */ initial_config.irqNb = BSP_IRQ_NUMBER; initial_config.defaultEntry = defaultIrq; initial_config.irqHdlTbl = rtemsIrq; initial_config.irqBase = BSP_LOWEST_OFFSET; initial_config.irqPrioTbl = irqPrioTable; printk("Call BSP_rtems_irq_mngt_set\n"); if (!BSP_rtems_irq_mngt_set(&initial_config)) { /* * put something here that will show the failure... */ BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); } #ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operationnal\n"); #endif }
/* * This code assumes the exceptions management setup has already * been done. We just need to replace the exceptions that will * be handled like interrupt. On mcp750/mpc750 and many PPC processors * this means the decrementer exception and the external exception. */ void BSP_rtems_irq_mng_init(unsigned cpuId) { #if !defined(mvme2100) int known_cpi_isa_bridge = 0; #endif int i; /* * First initialize the Interrupt management hardware */ #if defined(mvme2100) #ifdef TRACE_IRQ_INIT printk("Going to initialize EPIC interrupt controller (openpic compliant)\n"); #endif openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses); /* Speed up the serial interface; if it is too slow then we might get spurious * interrupts: * After an ISR clears the interrupt condition at the source/device, the wire * remains asserted during the propagation delay introduced by the serial interface * (something really stupid). If the ISR returns while the wire is not released * yet, then a spurious interrupt happens. * The book says we should be careful if the serial clock is > 33MHz. * Empirically, it seems that running it at 33MHz is fast enough. Otherwise, * we should introduce a delay in openpic_eoi(). * The maximal delay are 16 (serial) clock cycles. If the divisor is 8 * [power-up default] then the lag is 2us [66MHz SDRAM clock; I assume this * is equal to the bus frequency]. * FIXME: This should probably be a 8240-specific piece in 'openpic.c' */ { uint32_t eicr_val, ratio; /* On the 8240 this is the EICR register */ eicr_val = in_le32( &OpenPIC->Global.Global_Configuration1 ) & ~(7<<28); if ( (1<<27) & eicr_val ) { /* serial interface mode enabled */ /* round to nearest integer: * round(Bus_freq/33000000) = floor( 2*(Bus_freq/33e6) + 1 ) / 2 */ ratio = BSP_bus_frequency / 16500000 + 1; ratio >>= 2; /* EICR value is half actual divisor */ if ( 0==ratio ) ratio = 1; out_le32(&OpenPIC->Global.Global_Configuration1, eicr_val | ((ratio &7) << 28)); /* Delay in TB cycles (assuming TB runs at 1/4 of the bus frequency) */ openpic_set_eoi_delay( 16 * (2*ratio) / 4 ); } }
/* * This code assumes the exceptions management setup has already * been done. We just need to replace the exceptions that will * be handled like interrupt. On mcp750/mpc750 and many PPC processors * this means the decrementer exception and the external exception. */ void BSP_rtems_irq_mng_init(unsigned cpuId) { int i; /* * First initialize the Interrupt management hardware */ OpenPIC = (void*)PSIM.OpenPIC; openpic_init(1,0,0,16,0,0); /* * Initialize Rtems management interrupt table */ /* * re-init the rtemsIrq table */ for (i = 0; i < BSP_IRQ_NUMBER; i++) { rtemsIrq[i] = defaultIrq; rtemsIrq[i].name = i; } /* * Init initial Interrupt management config */ initial_config.irqNb = BSP_IRQ_NUMBER; initial_config.defaultEntry = defaultIrq; initial_config.irqHdlTbl = rtemsIrq; initial_config.irqBase = BSP_LOWEST_OFFSET; initial_config.irqPrioTbl = irqPrioTable; for (i = BSP_PCI_IRQ_LOWEST_OFFSET; i< BSP_PCI_IRQ_NUMBER; i++ ) { irqPrioTable[i] = 8; } if (!BSP_rtems_irq_mngt_set(&initial_config)) { /* * put something here that will show the failure... */ BSP_panic( "Unable to initialize RTEMS interrupt Management!!! System locked\n" ); } #ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operationnal\n"); #endif }
/* * Interrupt setup and service. The i8259 is cascaded from EPIC IRQ0, * IRQ1-4 map to PCI slots 1-4, IDE is on EPIC 7 and 8. */ static void __init sandpoint_init_IRQ(void) { int i; OpenPIC_InitSenses = sandpoint_openpic_initsenses; OpenPIC_NumInitSenses = sizeof (sandpoint_openpic_initsenses); /* * We need to tell openpic_set_sources where things actually are. * mpc10x_common will setup OpenPIC_Addr at ioremap(EUMB phys base + * EPIC offset (0x40000)); The EPIC IRQ Register Address Map - * Interrupt Source Configuration Registers gives these numbers * as offsets starting at 0x50200, we need to adjust occordinly. */ /* Map serial interrupt 0 */ openpic_set_sources(0, 1, OpenPIC_Addr + 0x10200); /* Map serial interrupts 2-5 */ openpic_set_sources(1, 4, OpenPIC_Addr + 0x10240); /* Map serial interrupts 8-9 */ openpic_set_sources(5, 2, OpenPIC_Addr + 0x10300); /* Skip reserved space and map i2c and DMA Ch[01] */ openpic_set_sources(7, 3, OpenPIC_Addr + 0x11020); /* Skip reserved space and map Message Unit Interrupt (I2O) */ openpic_set_sources(10, 1, OpenPIC_Addr + 0x110C0); openpic_init(NUM_8259_INTERRUPTS); /* The cascade is on EPIC IRQ 0 (Linux IRQ 16). */ openpic_hookup_cascade(16, "8259 cascade to EPIC", &i8259_irq); /* * openpic_init() has set up irq_desc[0-23] to be openpic * interrupts. We need to set irq_desc[0-15] to be 8259 interrupts. * We then need to request and enable the 8259 irq. */ for (i = 0; i < NUM_8259_INTERRUPTS; i++) irq_desc[i].handler = &i8259_pic; /* * The EPIC allows for a read in the range of 0xFEF00000 -> * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction. */ i8259_init(0xfef00000); }
/* * Interrupt setup and service. * Have MPIC on HAWK and cascaded 8259s on VIA 82586 cascaded to MPIC. */ static void __init mcpn765_init_IRQ(void) { int i; if ( ppc_md.progress ) ppc_md.progress("init_irq: enter", 0); openpic_init(NUM_8259_INTERRUPTS); openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade", i8259_irq); for(i=0; i < NUM_8259_INTERRUPTS; i++) irq_desc[i].handler = &i8259_pic; i8259_init(0); if ( ppc_md.progress ) ppc_md.progress("init_irq: exit", 0); return; }
void __init mpc85xx_ads_init_IRQ(void) { bd_t *binfo = (bd_t *) __res; /* Determine the Physical Address of the OpenPIC regs */ phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET; OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE); OpenPIC_InitSenses = mpc85xx_ads_openpic_initsenses; OpenPIC_NumInitSenses = sizeof (mpc85xx_ads_openpic_initsenses); /* Skip reserved space and internal sources */ openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); /* Map PIC IRQs 0-11 */ openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000); /* we let openpic interrupts starting from an offset, to * leave space for cascading interrupts underneath. */ openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET); return; }
static void __init pplus_init_IRQ(void) { int i; if (ppc_md.progress) ppc_md.progress("init_irq: enter", 0); OpenPIC_InitSenses = pplus_openpic_initsenses; OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses); if (OpenPIC_Addr != NULL) { openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000); openpic_init(NUM_8259_INTERRUPTS); openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade", i8259_irq); ppc_md.get_irq = openpic_get_irq; } i8259_init(0, 0); if (ppc_md.progress) ppc_md.progress("init_irq: exit", 0); }
__initfunc(void pmac_pic_init(void)) { int i; struct device_node *irqctrler; volatile struct pmac_irq_hw *addr; int second_irq; /* We first try to detect Apple's new Core99 chipset, since mac-io * is quite different on those machines and contains an IBM MPIC2. */ irqctrler = find_type_devices("open-pic"); if (irqctrler != NULL) { printk("PowerMac using OpenPIC irq controller\n"); if (irqctrler->n_addrs > 0) { #ifdef CONFIG_XMON struct device_node* pswitch; #endif /* CONFIG_XMON */ OpenPIC = (volatile struct OpenPIC *) ioremap(irqctrler->addrs[0].address, irqctrler->addrs[0].size); for ( i = 0 ; i < NR_IRQS ; i++ ) { irq_desc[i].ctl = &pmac_open_pic; irq_desc[i].level = 0; } openpic_init(1); has_openpic = 1; #ifdef CONFIG_XMON pswitch = find_devices("programmer-switch"); if (pswitch && pswitch->n_intrs) request_irq(pswitch->intrs[0].line, xmon_irq, 0, "NMI - XMON", 0); #endif /* CONFIG_XMON */ return; } irqctrler = NULL; } /* * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts, * 1998 G3 Series PowerBooks have 128, * other powermacs have 32. * The combo ethernet/modem card for the Powerstar powerbooks * (2400/3400/3500, ohare based) has a second ohare chip * effectively making a total of 64. */ max_irqs = max_real_irqs = 32; irqctrler = find_devices("mac-io"); if (irqctrler) { max_real_irqs = 64; if (irqctrler->next) max_irqs = 128; else max_irqs = 64; } for ( i = 0; i < max_real_irqs ; i++ ) irq_desc[i].ctl = &pmac_pic; /* get addresses of first controller */ if (irqctrler) { if (irqctrler->n_addrs > 0) { addr = ioremap(irqctrler->addrs[0].address, 0x40); addr += 2; for (i = 0; i < 2; ++i, --addr) pmac_irq_hw[i] = addr; } /* get addresses of second controller */ irqctrler = irqctrler->next; if (irqctrler && irqctrler->n_addrs > 0) { addr = ioremap(irqctrler->addrs[0].address, 0x40); addr += 2; for (i = 2; i < 4; ++i, --addr) pmac_irq_hw[i] = addr; } } /* PowerBooks 3400 and 3500 can have a second controller in a second ohare chip, on the combo ethernet/modem card */ if (machine_is_compatible("AAPL,3400/2400") || machine_is_compatible("AAPL,3500")) enable_second_ohare(); /* disable all interrupts in all controllers */ for (i = 0; i * 32 < max_irqs; ++i) out_le32(&pmac_irq_hw[i]->enable, 0); /* get interrupt line of secondary interrupt controller */ if (irqctrler) { second_irq = irqctrler->intrs[0].line; printk(KERN_INFO "irq: secondary controller on irq %d\n", (int)second_irq); if (device_is_compatible(irqctrler, "gatwick")) pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs); request_irq( second_irq, gatwick_action, SA_INTERRUPT, "interrupt cascade", 0 ); } for (i = max_real_irqs; i < max_irqs; i++) irq_desc[i].ctl = &gatwick_pic; printk("System has %d possible interrupts\n", max_irqs); if (max_irqs != max_real_irqs) printk(KERN_DEBUG "%d interrupts on main controller\n", max_real_irqs); #ifdef CONFIG_XMON request_irq(20, xmon_irq, 0, "NMI - XMON", 0); #endif /* CONFIG_XMON */ }
/* PowerPC Mac99 hardware initialisation */ static void ppc_core99_init (ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env = NULL, *envs[MAX_CPUS]; char *filename; qemu_irq *pic, **openpic_irqs; int unin_memory; int linux_boot, i; ram_addr_t ram_offset, bios_offset, vga_bios_offset; uint32_t kernel_base, kernel_size, initrd_base, initrd_size; PCIBus *pci_bus; MacIONVRAMState *nvr; int nvram_mem_index; int vga_bios_size, bios_size; qemu_irq *dummy_irq; int pic_mem_index, dbdma_mem_index, cuda_mem_index, escc_mem_index; int ppc_boot_device; int index; BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; void *dbdma; uint8_t *vga_bios_ptr; linux_boot = (kernel_filename != NULL); /* init CPUs */ if (cpu_model == NULL) cpu_model = "G4"; for (i = 0; i < smp_cpus; i++) { env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); #if 0 env->osi_call = vga_osi_call; #endif qemu_register_reset(&cpu_ppc_reset, env); envs[i] = env; } /* allocate RAM */ ram_offset = qemu_ram_alloc(ram_size); cpu_register_physical_memory(0, ram_size, ram_offset); /* allocate and load BIOS */ bios_offset = qemu_ram_alloc(BIOS_SIZE); if (bios_name == NULL) bios_name = PROM_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM); /* Load OpenBIOS (ELF) */ if (filename) { bios_size = load_elf(filename, 0, NULL, NULL, NULL); qemu_free(filename); } else { bios_size = -1; } if (bios_size < 0 || bios_size > BIOS_SIZE) { hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); exit(1); } /* allocate and load VGA BIOS */ vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE); vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset); filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME); if (filename) { vga_bios_size = load_image(filename, vga_bios_ptr + 8); qemu_free(filename); } else { vga_bios_size = -1; } if (vga_bios_size < 0) { /* if no bios is present, we can still work */ fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", VGABIOS_FILENAME); vga_bios_size = 0; } else { /* set a specific header (XXX: find real Apple format for NDRV drivers) */ vga_bios_ptr[0] = 'N'; vga_bios_ptr[1] = 'D'; vga_bios_ptr[2] = 'R'; vga_bios_ptr[3] = 'V'; cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size); vga_bios_size += 8; } if (linux_boot) { uint64_t lowaddr = 0; kernel_base = KERNEL_LOAD_ADDR; /* Now we can load the kernel. The first step tries to load the kernel supposing PhysAddr = 0x00000000. If that was wrong the kernel is loaded again, the new PhysAddr being computed from lowaddr. */ kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL); if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) { kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr, NULL, NULL, NULL); } if (kernel_size < 0) kernel_size = load_aout(kernel_filename, kernel_base, ram_size - kernel_base); if (kernel_size < 0) kernel_size = load_image_targphys(kernel_filename, kernel_base, ram_size - kernel_base); if (kernel_size < 0) { hw_error("qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } /* load initrd */ if (initrd_filename) { initrd_base = INITRD_LOAD_ADDR; initrd_size = load_image_targphys(initrd_filename, initrd_base, ram_size - initrd_base); if (initrd_size < 0) { hw_error("qemu: could not load initial ram disk '%s'\n", initrd_filename); exit(1); } } else { initrd_base = 0; initrd_size = 0; } ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; ppc_boot_device = '\0'; /* We consider that NewWorld PowerMac never have any floppy drive * For now, OHW cannot boot from the network. */ for (i = 0; boot_device[i] != '\0'; i++) { if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { ppc_boot_device = boot_device[i]; break; } } if (ppc_boot_device == '\0') { fprintf(stderr, "No valid boot device for Mac99 machine\n"); exit(1); } } isa_mem_base = 0x80000000; /* Register 8 MB of ISA IO space */ isa_mmio_init(0xf2000000, 0x00800000); /* UniN init */ unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL); cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); openpic_irqs[0] = qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); for (i = 0; i < smp_cpus; i++) { /* Mac99 IRQ connection between OpenPIC outputs pins * and PowerPC input pins */ switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_6xx: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_MCK] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; /* Not connected ? */ openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Check this */ openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; break; #if defined(TARGET_PPC64) case PPC_FLAGS_INPUT_970: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_MCK] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; /* Not connected ? */ openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Check this */ openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; break; #endif /* defined(TARGET_PPC64) */ default: hw_error("Bus model not supported on mac99 machine\n"); exit(1); } } pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL); pci_bus = pci_pmac_init(pic); /* init basic PC hardware */ pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size); /* XXX: suppress that */ dummy_irq = i8259_init(NULL); escc_mem_index = escc_init(0x80013000, dummy_irq[4], dummy_irq[5], serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); for(i = 0; i < nb_nics; i++) pci_nic_init(&nd_table[i], "ne2k_pci", NULL); if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { fprintf(stderr, "qemu: too many IDE bus\n"); exit(1); } for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); if (index != -1) hd[i] = drives_table[index].bdrv; else hd[i] = NULL; } dbdma = DBDMA_init(&dbdma_mem_index); pci_cmd646_ide_init(pci_bus, hd, 0); /* cuda also initialize ADB */ cuda_init(&cuda_mem_index, pic[0x19]); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem_index, dbdma_mem_index, cuda_mem_index, NULL, 0, NULL, escc_mem_index); if (usb_enabled) { usb_ohci_init_pci(pci_bus, 3, -1); } if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) graphic_depth = 15; /* The NewWorld NVRAM is not located in the MacIO device */ nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 1); pmac_format_nvram_partition(nvr, 0x2000); macio_nvram_map(nvr, 0xFFF04000); /* No PCI init: the BIOS will do it */ fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_MAC99); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); if (kernel_cmdline) { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); } else { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); } fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); }
/* PowerPC Mac99 hardware initialisation */ static void ppc_core99_init (ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { PowerPCCPU *cpu = NULL; CPUPPCState *env = NULL; char *filename; qemu_irq *pic, **openpic_irqs; MemoryRegion *unin_memory = g_new(MemoryRegion, 1); int linux_boot, i; MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); target_phys_addr_t kernel_base, initrd_base, cmdline_base = 0; long kernel_size, initrd_size; PCIBus *pci_bus; MacIONVRAMState *nvr; int bios_size; MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem, *escc_mem; MemoryRegion *escc_bar = g_new(MemoryRegion, 1); MemoryRegion *ide_mem[3]; int ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; void *dbdma; int machine_arch; linux_boot = (kernel_filename != NULL); /* init CPUs */ if (cpu_model == NULL) #ifdef TARGET_PPC64 cpu_model = "970fx"; #else cpu_model = "G4"; #endif for (i = 0; i < smp_cpus; i++) { cpu = cpu_ppc_init(cpu_model); if (cpu == NULL) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } env = &cpu->env; /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); qemu_register_reset(ppc_core99_reset, cpu); } /* allocate RAM */ memory_region_init_ram(ram, "ppc_core99.ram", ram_size); vmstate_register_ram_global(ram); memory_region_add_subregion(get_system_memory(), 0, ram); /* allocate and load BIOS */ memory_region_init_ram(bios, "ppc_core99.bios", BIOS_SIZE); vmstate_register_ram_global(bios); if (bios_name == NULL) bios_name = PROM_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); memory_region_set_readonly(bios, true); memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); /* Load OpenBIOS (ELF) */ if (filename) { bios_size = load_elf(filename, NULL, NULL, NULL, NULL, NULL, 1, ELF_MACHINE, 0); g_free(filename); } else { bios_size = -1; } if (bios_size < 0 || bios_size > BIOS_SIZE) { hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); exit(1); } if (linux_boot) { uint64_t lowaddr = 0; int bswap_needed; #ifdef BSWAP_NEEDED bswap_needed = 1; #else bswap_needed = 0; #endif kernel_base = KERNEL_LOAD_ADDR; kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); if (kernel_size < 0) kernel_size = load_aout(kernel_filename, kernel_base, ram_size - kernel_base, bswap_needed, TARGET_PAGE_SIZE); if (kernel_size < 0) kernel_size = load_image_targphys(kernel_filename, kernel_base, ram_size - kernel_base); if (kernel_size < 0) { hw_error("qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } /* load initrd */ if (initrd_filename) { initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); initrd_size = load_image_targphys(initrd_filename, initrd_base, ram_size - initrd_base); if (initrd_size < 0) { hw_error("qemu: could not load initial ram disk '%s'\n", initrd_filename); exit(1); } cmdline_base = round_page(initrd_base + initrd_size); } else { initrd_base = 0; initrd_size = 0; cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); } ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; ppc_boot_device = '\0'; /* We consider that NewWorld PowerMac never have any floppy drive * For now, OHW cannot boot from the network. */ for (i = 0; boot_device[i] != '\0'; i++) { if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { ppc_boot_device = boot_device[i]; break; } } if (ppc_boot_device == '\0') { fprintf(stderr, "No valid boot device for Mac99 machine\n"); exit(1); } } /* Register 8 MB of ISA IO space */ isa_mmio_init(0xf2000000, 0x00800000); /* UniN init */ memory_region_init_io(unin_memory, &unin_ops, NULL, "unin", 0x1000); memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); openpic_irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); for (i = 0; i < smp_cpus; i++) { /* Mac99 IRQ connection between OpenPIC outputs pins * and PowerPC input pins */ switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_6xx: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_MCK] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; /* Not connected ? */ openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Check this */ openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; break; #if defined(TARGET_PPC64) case PPC_FLAGS_INPUT_970: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_MCK] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; /* Not connected ? */ openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Check this */ openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; break; #endif /* defined(TARGET_PPC64) */ default: hw_error("Bus model not supported on mac99 machine\n"); exit(1); } } pic = openpic_init(&pic_mem, smp_cpus, openpic_irqs, NULL); if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { /* 970 gets a U3 bus */ pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); machine_arch = ARCH_MAC99_U3; } else { pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); machine_arch = ARCH_MAC99; } /* init basic PC hardware */ pci_vga_init(pci_bus); escc_mem = escc_init(0, pic[0x25], pic[0x24], serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); memory_region_init_alias(escc_bar, "escc-bar", escc_mem, 0, memory_region_size(escc_mem)); for(i = 0; i < nb_nics; i++) pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); ide_drive_get(hd, MAX_IDE_BUS); dbdma = DBDMA_init(&dbdma_mem); /* We only emulate 2 out of 3 IDE controllers for now */ ide_mem[0] = NULL; ide_mem[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]); ide_mem[2] = pmac_ide_init(&hd[MAX_IDE_DEVS], pic[0x0e], dbdma, 0x1a, pic[0x02]); /* cuda also initialize ADB */ if (machine_arch == ARCH_MAC99_U3) { usb_enabled = 1; } cuda_init(&cuda_mem, pic[0x19]); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem, dbdma_mem, cuda_mem, NULL, 3, ide_mem, escc_bar); if (usb_enabled) { pci_create_simple(pci_bus, -1, "pci-ohci"); } /* U3 needs to use USB for input because Linux doesn't support via-cuda on PPC64 */ if (machine_arch == ARCH_MAC99_U3) { usbdevice_create("keyboard"); usbdevice_create("mouse"); } if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) graphic_depth = 15; /* The NewWorld NVRAM is not located in the MacIO device */ nvr = macio_nvram_init(0x2000, 1); pmac_format_nvram_partition(nvr, 0x2000); macio_nvram_setup_bar(nvr, get_system_memory(), 0xFFF04000); /* No PCI init: the BIOS will do it */ fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); if (kernel_cmdline) { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); } else { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); } fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); if (kvm_enabled()) { #ifdef CONFIG_KVM uint8_t *hypercall; fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); hypercall = g_malloc(16); kvmppc_get_hypercall(env, hypercall, 16); fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); #endif } else { fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec()); } qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); }
static status_t openpic_init_driver(device_node *node, void **cookie) { // OK, this module is broken for now. But it compiles. return B_ERROR; openpic_info *info = new(nothrow) openpic_info; if (!info) return B_NO_MEMORY; ObjectDeleter<openpic_info> infoDeleter(info); info->node = node; // get interface to PCI device void *aCookie; void *anotherCookie; // possibly the same cookie. driver_module_info *driver; status_t status = sDeviceManager->get_driver(sDeviceManager->get_parent_node(node), &driver, &aCookie); if (status != B_OK) return status; driver->init_driver(node, &anotherCookie); /* status = sDeviceManager->init_driver( sDeviceManager->get_parent(node), NULL, (driver_module_info**)&info->pci, (void**)&info->device); if (status != B_OK) return status; */ // get the pci info for the device pci_info pciInfo; info->pci->get_pci_info(info->device, &pciInfo); // find supported device info info->supported_device = openpic_check_supported_device(pciInfo.vendor_id, pciInfo.device_id); if (!info->supported_device) { dprintf("openpic: device (0x%04hx:0x%04hx) not supported\n", pciInfo.vendor_id, pciInfo.device_id); return B_ERROR; } dprintf("openpic: found supported device: %s (0x%04hx:0x%04hx)\n", info->supported_device->name, pciInfo.vendor_id, pciInfo.device_id); // get register space addr_t physicalRegisterBase = pciInfo.u.h0.base_registers[0]; uint32 registerSpaceSize = pciInfo.u.h0.base_register_sizes[0]; if (registerSpaceSize < info->supported_device->register_offset || registerSpaceSize - info->supported_device->register_offset < OPENPIC_MIN_REGISTER_SPACE_SIZE) { dprintf("openpic: register space too small\n"); } physicalRegisterBase += info->supported_device->register_offset; registerSpaceSize -= info->supported_device->register_offset; if (registerSpaceSize > OPENPIC_MAX_REGISTER_SPACE_SIZE) registerSpaceSize = OPENPIC_MAX_REGISTER_SPACE_SIZE; // map register space void *virtualRegisterBase = NULL; area_id registerArea = map_physical_memory("openpic registers", (void*)physicalRegisterBase, registerSpaceSize, B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, &virtualRegisterBase); if (registerArea < 0) return info->register_area; info->physical_registers = physicalRegisterBase; info->register_space_size = registerSpaceSize; info->register_area = registerArea; info->virtual_registers = (addr_t)virtualRegisterBase; // init the controller status = openpic_init(info); if (status != B_OK) return status; // keep the info infoDeleter.Detach(); *cookie = info; dprintf("openpic_init_driver(): Successfully initialized!\n"); return B_OK; }
static void __init prpmc750_init_IRQ(void) { openpic_init(0); }
/* PowerPC Mac99 hardware initialisation */ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size, const char *boot_device, DisplayState *ds, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env = NULL, *envs[MAX_CPUS]; char buf[1024]; qemu_irq *pic, **openpic_irqs; int unin_memory; int linux_boot, i; unsigned long bios_offset, vga_bios_offset; uint32_t kernel_base, kernel_size, initrd_base, initrd_size; PCIBus *pci_bus; nvram_t nvram; #if 0 MacIONVRAMState *nvr; int nvram_mem_index; #endif m48t59_t *m48t59; int vga_bios_size, bios_size; qemu_irq *dummy_irq; int pic_mem_index, dbdma_mem_index, cuda_mem_index; int ide_mem_index[2]; int ppc_boot_device; int index; BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; linux_boot = (kernel_filename != NULL); /* init CPUs */ if (cpu_model == NULL) cpu_model = "default"; for (i = 0; i < smp_cpus; i++) { env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); #if 0 env->osi_call = vga_osi_call; #endif qemu_register_reset(&cpu_ppc_reset, env); register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); envs[i] = env; } if (env->nip < 0xFFF80000) { /* Special test for PowerPC 601: * the boot vector is at 0xFFF00100, then we need a 1MB BIOS. * But the NVRAM is located at 0xFFF04000... */ cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n"); } /* allocate RAM */ cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); /* allocate and load BIOS */ bios_offset = ram_size + vga_ram_size; if (bios_name == NULL) bios_name = BIOS_FILENAME; snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); bios_size = load_image(buf, phys_ram_base + bios_offset); if (bios_size < 0 || bios_size > BIOS_SIZE) { cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf); exit(1); } bios_size = (bios_size + 0xfff) & ~0xfff; if (bios_size > 0x00080000) { /* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */ cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n"); } cpu_register_physical_memory((uint32_t)(-bios_size), bios_size, bios_offset | IO_MEM_ROM); /* allocate and load VGA BIOS */ vga_bios_offset = bios_offset + bios_size; snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8); if (vga_bios_size < 0) { /* if no bios is present, we can still work */ fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf); vga_bios_size = 0; } else { /* set a specific header (XXX: find real Apple format for NDRV drivers) */ phys_ram_base[vga_bios_offset] = 'N'; phys_ram_base[vga_bios_offset + 1] = 'D'; phys_ram_base[vga_bios_offset + 2] = 'R'; phys_ram_base[vga_bios_offset + 3] = 'V'; cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4), vga_bios_size); vga_bios_size += 8; } vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff; if (linux_boot) { kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); if (kernel_size < 0) { cpu_abort(env, "qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } /* load initrd */ if (initrd_filename) { initrd_base = INITRD_LOAD_ADDR; initrd_size = load_image(initrd_filename, phys_ram_base + initrd_base); if (initrd_size < 0) { cpu_abort(env, "qemu: could not load initial ram disk '%s'\n", initrd_filename); exit(1); } } else { initrd_base = 0; initrd_size = 0; } ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; ppc_boot_device = '\0'; /* We consider that NewWorld PowerMac never have any floppy drive * For now, OHW cannot boot from the network. */ for (i = 0; boot_device[i] != '\0'; i++) { if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { ppc_boot_device = boot_device[i]; break; } } if (ppc_boot_device == '\0') { fprintf(stderr, "No valid boot device for Mac99 machine\n"); exit(1); } } isa_mem_base = 0x80000000; /* Register 8 MB of ISA IO space */ isa_mmio_init(0xf2000000, 0x00800000); /* UniN init */ unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL); cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); openpic_irqs[0] = qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); for (i = 0; i < smp_cpus; i++) { /* Mac99 IRQ connection between OpenPIC outputs pins * and PowerPC input pins */ switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_6xx: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_MCK] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; /* Not connected ? */ openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Check this */ openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; break; #if defined(TARGET_PPC64) case PPC_FLAGS_INPUT_970: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_MCK] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; /* Not connected ? */ openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Check this */ openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; break; #endif /* defined(TARGET_PPC64) */ default: cpu_abort(env, "Bus model not supported on mac99 machine\n"); exit(1); } } pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL); pci_bus = pci_pmac_init(pic); /* init basic PC hardware */ pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size, vga_bios_offset, vga_bios_size); /* XXX: suppress that */ dummy_irq = i8259_init(NULL); /* XXX: use Mac Serial port */ serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]); for(i = 0; i < nb_nics; i++) { if (!nd_table[i].model) nd_table[i].model = "ne2k_pci"; pci_nic_init(pci_bus, &nd_table[i], -1); } if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { fprintf(stderr, "qemu: too many IDE bus\n"); exit(1); } for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); if (index != -1) hd[i] = drives_table[index].bdrv; else hd[i] = NULL; } #if 1 ide_mem_index[0] = pmac_ide_init(&hd[0], pic[0x13]); ide_mem_index[1] = pmac_ide_init(&hd[2], pic[0x14]); #else pci_cmd646_ide_init(pci_bus, &hd[0], 0); #endif /* cuda also initialize ADB */ cuda_init(&cuda_mem_index, pic[0x19]); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); dbdma_init(&dbdma_mem_index); macio_init(pci_bus, 0x0022, 0, pic_mem_index, dbdma_mem_index, cuda_mem_index, NULL, 2, ide_mem_index); if (usb_enabled) { usb_ohci_init_pci(pci_bus, 3, -1); } if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) graphic_depth = 15; #if 0 /* XXX: this is ugly but needed for now, or OHW won't boot */ /* The NewWorld NVRAM is not located in the MacIO device */ nvr = macio_nvram_init(&nvram_mem_index, 0x2000); pmac_format_nvram_partition(nvr, 0x2000); macio_nvram_map(nvr, 0xFFF04000); nvram.opaque = nvr; nvram.read_fn = &macio_nvram_read; nvram.write_fn = &macio_nvram_write; #else m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59); nvram.opaque = m48t59; nvram.read_fn = &m48t59_read; nvram.write_fn = &m48t59_write; #endif PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "MAC99", ram_size, ppc_boot_device, kernel_base, kernel_size, kernel_cmdline, initrd_base, initrd_size, /* XXX: need an option to load a NVRAM image */ 0, graphic_width, graphic_height, graphic_depth); /* No PCI init: the BIOS will do it */ /* Special port to get debug messages from Open-Firmware */ register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); }
/* * This code assumes the exceptions management setup has already * been done. We just need to replace the exceptions that will * be handled like interrupt. On mcp750/mpc750 and many PPC processors * this means the decrementer exception and the external exception. */ void BSP_rtems_irq_mng_init(unsigned cpuId) { #if BSP_ISA_IRQ_NUMBER > 0 && !defined(mvme2100) int known_cpi_isa_bridge = 0; #endif int i; /* * First initialize the Interrupt management hardware */ #if defined(mvme2100) #ifdef TRACE_IRQ_INIT printk("Going to initialize EPIC interrupt controller (openpic compliant)\n"); #endif /* EPIC sources don't start at the regular place; define appropriate offset * prior to initializing the PIC. */ openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses, 16, 16, BSP_bus_frequency); #else #if BSP_PCI_IRQ_NUMBER > 0 #ifdef TRACE_IRQ_INIT printk("Going to initialize raven interrupt controller (openpic compliant)\n"); #endif openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 0, 0); #ifdef TRACE_IRQ_INIT printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n"); #endif #endif #if BSP_ISA_IRQ_NUMBER > 0 if ( currentBoard == MESQUITE ) { #ifndef qemu VIA_isa_bridge_interrupts_setup(); #endif known_cpi_isa_bridge = 1; } if ( currentBoard == MVME_2300 ) { /* nothing to do for W83C553 bridge */ known_cpi_isa_bridge = 1; } if ( currentBoard == MTX_WO_PP || currentBoard == MTX_W_PP ) { /* W83C554, don't to anything at the moment. gregm 11/6/2002 */ known_cpi_isa_bridge = 1; } if (!known_cpi_isa_bridge) { printk("Please add code for PCI/ISA bridge init to libbsp/powerpc/shared/irq/irq_init.c\n"); printk("If your card works correctly please add a test and set known_cpi_isa_bridge to true\n"); printk("currentBoard = %i\n", currentBoard); } #ifdef TRACE_IRQ_INIT printk("Going to initialize the ISA PC legacy IRQ management hardware\n"); #endif BSP_i8259s_init(); #endif #endif /* * Initialize RTEMS management interrupt table */ /* * re-init the rtemsIrq table */ for (i = 0; i < BSP_IRQ_NUMBER; i++) { rtemsIrq[i] = defaultIrq; rtemsIrq[i].name = i; } /* * Init initial Interrupt management config */ initial_config.irqNb = BSP_IRQ_NUMBER; initial_config.defaultEntry = defaultIrq; initial_config.irqHdlTbl = rtemsIrq; initial_config.irqBase = BSP_LOWEST_OFFSET; initial_config.irqPrioTbl = irqPrioTable; if (!BSP_rtems_irq_mngt_set(&initial_config)) { /* * put something here that will show the failure... */ BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); } #ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operational\n"); #endif }
/* PowerPC Mac99 hardware initialisation */ static void ppc_core99_init (ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env = NULL, *envs[MAX_CPUS]; char *filename; qemu_irq *pic, **openpic_irqs; int unin_memory; int linux_boot, i; ram_addr_t ram_offset, bios_offset, vga_bios_offset; uint32_t kernel_base, kernel_size, initrd_base, initrd_size; PCIBus *pci_bus; MacIONVRAMState *nvr; int nvram_mem_index; int vga_bios_size, bios_size; int pic_mem_index, dbdma_mem_index, cuda_mem_index, escc_mem_index; int ide_mem_index[3]; int ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; void *dbdma; uint8_t *vga_bios_ptr; int machine_arch; linux_boot = (kernel_filename != NULL); /* init CPUs */ if (cpu_model == NULL) #ifdef TARGET_PPC64 cpu_model = "970fx"; #else cpu_model = "G4"; #endif for (i = 0; i < smp_cpus; i++) { env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); #if 0 env->osi_call = vga_osi_call; #endif qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); envs[i] = env; } /* allocate RAM */ ram_offset = qemu_ram_alloc(NULL, "ppc_core99.ram", ram_size); cpu_register_physical_memory(0, ram_size, ram_offset); /* allocate and load BIOS */ bios_offset = qemu_ram_alloc(NULL, "ppc_core99.bios", BIOS_SIZE); if (bios_name == NULL) bios_name = PROM_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM); /* Load OpenBIOS (ELF) */ if (filename) { bios_size = load_elf(filename, NULL, NULL, NULL, NULL, NULL, 1, ELF_MACHINE, 0); qemu_free(filename); } else { bios_size = -1; } if (bios_size < 0 || bios_size > BIOS_SIZE) { hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); exit(1); } /* allocate and load VGA BIOS */ vga_bios_offset = qemu_ram_alloc(NULL, "ppc_core99.vbios", VGA_BIOS_SIZE); vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset); filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME); if (filename) { vga_bios_size = load_image(filename, vga_bios_ptr + 8); qemu_free(filename); } else { vga_bios_size = -1; } if (vga_bios_size < 0) { /* if no bios is present, we can still work */ fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", VGABIOS_FILENAME); vga_bios_size = 0; } else { /* set a specific header (XXX: find real Apple format for NDRV drivers) */ vga_bios_ptr[0] = 'N'; vga_bios_ptr[1] = 'D'; vga_bios_ptr[2] = 'R'; vga_bios_ptr[3] = 'V'; cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size); vga_bios_size += 8; /* Round to page boundary */ vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; } if (linux_boot) { uint64_t lowaddr = 0; int bswap_needed; #ifdef BSWAP_NEEDED bswap_needed = 1; #else bswap_needed = 0; #endif kernel_base = KERNEL_LOAD_ADDR; kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); if (kernel_size < 0) kernel_size = load_aout(kernel_filename, kernel_base, ram_size - kernel_base, bswap_needed, TARGET_PAGE_SIZE); if (kernel_size < 0) kernel_size = load_image_targphys(kernel_filename, kernel_base, ram_size - kernel_base); if (kernel_size < 0) { hw_error("qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } /* load initrd */ if (initrd_filename) { initrd_base = INITRD_LOAD_ADDR; initrd_size = load_image_targphys(initrd_filename, initrd_base, ram_size - initrd_base); if (initrd_size < 0) { hw_error("qemu: could not load initial ram disk '%s'\n", initrd_filename); exit(1); } } else { initrd_base = 0; initrd_size = 0; } ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; ppc_boot_device = '\0'; /* We consider that NewWorld PowerMac never have any floppy drive * For now, OHW cannot boot from the network. */ for (i = 0; boot_device[i] != '\0'; i++) { if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { ppc_boot_device = boot_device[i]; break; } } if (ppc_boot_device == '\0') { fprintf(stderr, "No valid boot device for Mac99 machine\n"); exit(1); } } isa_mem_base = 0x80000000; /* Register 8 MB of ISA IO space */ isa_mmio_init(0xf2000000, 0x00800000, 1); /* UniN init */ unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL); cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); openpic_irqs[0] = qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); for (i = 0; i < smp_cpus; i++) { /* Mac99 IRQ connection between OpenPIC outputs pins * and PowerPC input pins */ switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_6xx: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_MCK] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; /* Not connected ? */ openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Check this */ openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; break; #if defined(TARGET_PPC64) case PPC_FLAGS_INPUT_970: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_MCK] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; /* Not connected ? */ openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Check this */ openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; break; #endif /* defined(TARGET_PPC64) */ default: hw_error("Bus model not supported on mac99 machine\n"); exit(1); } } pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL); if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { /* 970 gets a U3 bus */ pci_bus = pci_pmac_u3_init(pic); machine_arch = ARCH_MAC99_U3; } else { pci_bus = pci_pmac_init(pic); machine_arch = ARCH_MAC99; } /* init basic PC hardware */ pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size); escc_mem_index = escc_init(0x80013000, pic[0x25], pic[0x24], serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); for(i = 0; i < nb_nics; i++) pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { fprintf(stderr, "qemu: too many IDE bus\n"); exit(1); } dbdma = DBDMA_init(&dbdma_mem_index); /* We only emulate 2 out of 3 IDE controllers for now */ ide_mem_index[0] = -1; hd[0] = drive_get(IF_IDE, 0, 0); hd[1] = drive_get(IF_IDE, 0, 1); ide_mem_index[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]); hd[0] = drive_get(IF_IDE, 1, 0); hd[1] = drive_get(IF_IDE, 1, 1); ide_mem_index[2] = pmac_ide_init(hd, pic[0x0e], dbdma, 0x1a, pic[0x02]); /* cuda also initialize ADB */ if (machine_arch == ARCH_MAC99_U3) { usb_enabled = 1; } cuda_init(&cuda_mem_index, pic[0x19]); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem_index, dbdma_mem_index, cuda_mem_index, NULL, 3, ide_mem_index, escc_mem_index); if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); } /* U3 needs to use USB for input because Linux doesn't support via-cuda on PPC64 */ if (machine_arch == ARCH_MAC99_U3) { usbdevice_create("keyboard"); usbdevice_create("mouse"); } if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) graphic_depth = 15; /* The NewWorld NVRAM is not located in the MacIO device */ nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 1); pmac_format_nvram_partition(nvr, 0x2000); macio_nvram_map(nvr, 0xFFF04000); /* No PCI init: the BIOS will do it */ fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); if (kernel_cmdline) { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); } else { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); } fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); if (kvm_enabled()) { #ifdef CONFIG_KVM uint8_t *hypercall; fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); hypercall = qemu_malloc(16); kvmppc_get_hypercall(env, hypercall, 16); fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); #endif } else { fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec()); } qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); }