static int exynos7_init_disp_table(struct device *dev, struct devfreq_data_disp *data)
{
unsigned int i;
unsigned int ret;
unsigned int freq;
unsigned int volt;
for (i = 0; i < data->max_state; ++i) {
freq = devfreq_disp_opp_list[i].freq;
volt = get_match_volt(ID_ISP, freq);
if (!volt)
volt = devfreq_disp_opp_list[i].volt;
devfreq_disp_opp_list[i].volt = volt;
exynos7_devfreq_disp_profile.freq_table[i] = freq;
ret = opp_add(dev, freq, volt);
if (ret) {
pr_err("DEVFREQ(DISP) : Failed to add opp entries %uKhz, %uuV\n", freq, volt);
return ret;
} else {
pr_info("DEVFREQ(DISP) : %7uKhz, %7uuV\n", freq, volt);
}
}
opp_disable(dev, devfreq_disp_opp_list[0].freq);
opp_disable(dev, devfreq_disp_opp_list[1].freq);
data->volt_of_avail_max_freq = get_volt_of_avail_max_freq(dev);
pr_info("DEVFREQ(DISP) : voltage of available max freq : %7uuV\n",
data->volt_of_avail_max_freq);
return 0;
}
static void __init beagle_opp_init(void)
{
int r = 0;
/* Initialize the omap3 opp table */
if (omap3_opp_init()) {
pr_err("%s: opp default init failed\n", __func__);
return;
}
/* Custom OPP enabled for XM */
if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM || omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XMC) {
struct omap_hwmod *mh = omap_hwmod_lookup("mpu");
struct omap_hwmod *dh = omap_hwmod_lookup("iva");
struct device *dev;
if (!mh || !dh) {
pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
__func__, mh, dh);
r = -EINVAL;
} else {
/* Enable MPU 1GHz and lower opps */
dev = &mh->od->pdev.dev;
r = opp_enable(dev, 800000000);
r |= opp_enable(dev, 1000000000);
/* Enable IVA 800MHz and lower opps */
dev = &dh->od->pdev.dev;
r |= opp_enable(dev, 660000000);
r |= opp_enable(dev, 800000000);
}
if (r) {
pr_err("%s: failed to enable higher opp %d\n",
__func__, r);
/*
* Cleanup - disable the higher freqs - we dont care
* about the results
*/
dev = &mh->od->pdev.dev;
opp_disable(dev, 800000000);
opp_disable(dev, 1000000000);
dev = &dh->od->pdev.dev;
opp_disable(dev, 660000000);
opp_disable(dev, 800000000);
} else {
pr_err("%s: turbo OPPs enabled!\n", __func__);
}
}
}
static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
{
struct device_node *np;
void __iomem *base;
u32 val;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
if (!np) {
pr_warn("failed to find ocotp node\n");
return;
}
base = of_iomap(np, 0);
if (!base) {
pr_warn("failed to map ocotp\n");
goto put_node;
}
val = readl_relaxed(base + OCOTP_CFG3);
val >>= OCOTP_CFG3_SPEED_SHIFT;
if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
if (opp_disable(cpu_dev, 1200000000))
pr_warn("failed to disable 1.2 GHz OPP\n");
put_node:
of_node_put(np);
}
static void __init overo_opp_init(void)
{
int r = 0;
/* Initialize the omap3 opp table */
if (omap3_opp_init()) {
pr_err("%s: opp default init failed\n", __func__);
return;
}
/* Custom OPP enabled for 36/3730 */
if (cpu_is_omap3630()) {
struct device *mpu_dev, *iva_dev;
mpu_dev = omap_device_get_by_hwmod_name("mpu");
if (omap3_has_iva())
iva_dev = omap_device_get_by_hwmod_name("iva");
if (!mpu_dev) {
pr_err("%s: Aiee.. no mpu device? %p\n",
__func__, mpu_dev);
return;
}
/* Enable MPU 1GHz and lower opps */
r = opp_enable(mpu_dev, 800000000);
r |= opp_enable(mpu_dev, 1000000000);
if (omap3_has_iva()) {
/* Enable IVA 800MHz and lower opps */
r |= opp_enable(iva_dev, 660000000);
r |= opp_enable(iva_dev, 800000000);
}
if (r) {
pr_err("%s: failed to enable higher opp %d\n",
__func__, r);
opp_disable(mpu_dev, 800000000);
opp_disable(mpu_dev, 1000000000);
if (omap3_has_iva()) {
opp_disable(iva_dev, 660000000);
opp_disable(iva_dev, 800000000);
}
}
}
return;
}
static int __init beagle_opp_init(void)
{
int r = 0;
if (!machine_is_omap3_beagle())
return 0;
/* Initialize the omap3 opp table if not already created. */
r = omap3_opp_init();
if (r < 0 && (r != -EEXIST)) {
pr_err("%s: opp default init failed\n", __func__);
return r;
}
/* Custom OPP enabled for all xM versions */
if (cpu_is_omap3630()) {
struct device *mpu_dev, *iva_dev;
mpu_dev = get_cpu_device(0);
iva_dev = omap_device_get_by_hwmod_name("iva");
if (IS_ERR(mpu_dev) || IS_ERR(iva_dev)) {
pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
__func__, mpu_dev, iva_dev);
return -ENODEV;
}
/* Enable MPU 1GHz and lower opps */
r = opp_enable(mpu_dev, 800000000);
/* TODO: MPU 1GHz needs SR and ABB */
/* Enable IVA 800MHz and lower opps */
r |= opp_enable(iva_dev, 660000000);
/* TODO: DSP 800MHz needs SR and ABB */
if (r) {
pr_err("%s: failed to enable higher opp %d\n",
__func__, r);
/*
* Cleanup - disable the higher freqs - we dont care
* about the results
*/
opp_disable(mpu_dev, 800000000);
opp_disable(iva_dev, 660000000);
}
}
return 0;
}
static void __init beagle_opp_init(void)
{
int r = 0;
/* Initialize the omap3 opp table */
if (omap3_opp_init()) {
pr_err("%s: opp default init failed\n", __func__);
return;
}
/* Custom OPP enabled for all xM versions */
if (cpu_is_omap3630()) {
struct omap_hwmod *mh = omap_hwmod_lookup("mpu");
struct omap_hwmod *dh = omap_hwmod_lookup("iva");
struct device *dev;
if (!mh || !dh) {
pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
__func__, mh, dh);
return;
}
/* Enable MPU 1GHz and lower opps */
dev = &mh->od->pdev.dev;
r = opp_enable(dev, 800000000);
/* TODO: MPU 1GHz needs SR and ABB */
/* Enable IVA 800MHz and lower opps */
dev = &dh->od->pdev.dev;
r |= opp_enable(dev, 660000000);
/* TODO: DSP 800MHz needs SR and ABB */
if (r) {
pr_err("%s: failed to enable higher opp %d\n",
__func__, r);
/*
* Cleanup - disable the higher freqs - we dont care
* about the results
*/
dev = &mh->od->pdev.dev;
opp_disable(dev, 800000000);
dev = &dh->od->pdev.dev;
opp_disable(dev, 660000000);
}
}
return;
}
static void __init beagle_opp_init(void)
{
int r = 0;
/* Initialize the omap3 opp table */
if (omap3_opp_init()) {
pr_err("%s: opp default init failed\n", __func__);
return;
}
/* Custom OPP enabled for all xM versions */
if (cpu_is_omap3630()) {
struct device *mpu_dev, *iva_dev;
mpu_dev = omap_device_get_by_hwmod_name("mpu");
iva_dev = omap_device_get_by_hwmod_name("iva");
if (!mpu_dev || !iva_dev) {
pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
__func__, mpu_dev, iva_dev);
return;
}
/* Enable MPU 1GHz and lower opps */
r = opp_enable(mpu_dev, 800000000);
/* TODO: MPU 1GHz needs SR and ABB */
/* Enable IVA 800MHz and lower opps */
r |= opp_enable(iva_dev, 660000000);
/* TODO: DSP 800MHz needs SR and ABB */
if (r) {
pr_err("%s: failed to enable higher opp %d\n",
__func__, r);
/*
* Cleanup - disable the higher freqs - we dont care
* about the results
*/
opp_disable(mpu_dev, 800000000);
opp_disable(iva_dev, 660000000);
}
}
return;
}
/**
* omap_init_opp_table() - Initialize opp table as per the CPU type
* @opp_def: opp default list for this silicon
* @opp_def_size: number of opp entries for this silicon
*
* Register the initial OPP table with the OPP library based on the CPU
* type. This is meant to be used only by SoC specific registration.
*/
int __init omap_init_opp_table(struct omap_opp_def *opp_def,
u32 opp_def_size)
{
int i, r;
struct clk *clk;
long round_rate;
if (!opp_def || !opp_def_size) {
pr_err("%s: invalid params!\n", __func__);
return -EINVAL;
}
/*
* Initialize only if not already initialized even if the previous
* call failed, because, no reason we'd succeed again.
*/
if (omap_table_init)
return -EEXIST;
omap_table_init = 1;
/* Lets now register with OPP library */
for (i = 0; i < opp_def_size; i++, opp_def++) {
struct omap_hwmod *oh;
struct device *dev;
if (!opp_def->hwmod_name) {
WARN(1, "%s: NULL name of omap_hwmod, failing"
" [%d].\n", __func__, i);
return -EINVAL;
}
oh = omap_hwmod_lookup(opp_def->hwmod_name);
if (!oh || !oh->od) {
WARN(1, "%s: no hwmod or odev for %s, [%d] "
"cannot add OPPs.\n", __func__,
opp_def->hwmod_name, i);
return -EINVAL;
}
dev = &oh->od->pdev.dev;
clk = omap_clk_get_by_name(opp_def->clk_name);
if (clk) {
round_rate = clk_round_rate(clk, opp_def->freq);
if (round_rate > 0) {
opp_def->freq = round_rate;
} else {
WARN(1, "%s: round_rate for clock %s failed\n",
__func__, opp_def->clk_name);
return -EINVAL; /* skip Bad OPP */
}
} else {
WARN(1, "%s: No clock by name %s found\n", __func__,
opp_def->clk_name);
return -EINVAL; /* skip Bad OPP */
}
r = opp_add(dev, opp_def->freq, opp_def->u_volt);
if (r) {
dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
"result=%d\n",
__func__, opp_def->freq,
opp_def->hwmod_name, i, r);
} else {
if (!opp_def->default_available)
r = opp_disable(dev, opp_def->freq);
if (r)
dev_err(dev, "%s: disable %ld failed for %s "
"[%d] result=%d\n",
__func__, opp_def->freq,
opp_def->hwmod_name, i, r);
r = omap_dvfs_register_device(dev,
opp_def->voltdm_name, opp_def->clk_name);
if (r)
dev_err(dev, "%s:%s:err dvfs register %d %d\n",
__func__, opp_def->hwmod_name, r, i);
}
}
return 0;
}
int exynos5250_init(struct device *dev, struct busfreq_data *data)
{
unsigned int i, tmp;
unsigned long maxfreq = ULONG_MAX;
unsigned long minfreq = 0;
unsigned long cdrexfreq;
unsigned long lrbusfreq;
struct clk *clk;
int ret;
/* Enable pause function for DREX2 DVFS */
drex2_pause_ctrl = __raw_readl(EXYNOS5_DREX2_PAUSE);
drex2_pause_ctrl |= DMC_PAUSE_ENABLE;
__raw_writel(drex2_pause_ctrl, EXYNOS5_DREX2_PAUSE);
clk = clk_get(NULL, "mclk_cdrex");
if (IS_ERR(clk)) {
dev_err(dev, "Fail to get mclk_cdrex clock");
ret = PTR_ERR(clk);
return ret;
}
cdrexfreq = clk_get_rate(clk) / 1000;
clk_put(clk);
clk = clk_get(NULL, "aclk_266");
if (IS_ERR(clk)) {
dev_err(dev, "Fail to get aclk_266 clock");
ret = PTR_ERR(clk);
return ret;
}
lrbusfreq = clk_get_rate(clk) / 1000;
clk_put(clk);
if (cdrexfreq == 800000) {
clkdiv_cdrex = clkdiv_cdrex_for800;
exynos5_busfreq_table_mif = exynos5_busfreq_table_for800;
exynos5_mif_volt = exynos5_mif_volt_for800;
} else if (cdrexfreq == 666857) {
clkdiv_cdrex = clkdiv_cdrex_for667;
exynos5_busfreq_table_mif = exynos5_busfreq_table_for667;
exynos5_mif_volt = exynos5_mif_volt_for667;
} else if (cdrexfreq == 533000) {
clkdiv_cdrex = clkdiv_cdrex_for533;
exynos5_busfreq_table_mif = exynos5_busfreq_table_for533;
exynos5_mif_volt = exynos5_mif_volt_for533;
} else if (cdrexfreq == 400000) {
clkdiv_cdrex = clkdiv_cdrex_for400;
exynos5_busfreq_table_mif = exynos5_busfreq_table_for400;
exynos5_mif_volt = exynos5_mif_volt_for400;
} else {
dev_err(dev, "Don't support cdrex table\n");
return -EINVAL;
}
tmp = __raw_readl(EXYNOS5_CLKDIV_LEX);
for (i = LV_0; i < LV_INT_END; i++) {
tmp &= ~(EXYNOS5_CLKDIV_LEX_ATCLK_LEX_MASK | EXYNOS5_CLKDIV_LEX_PCLK_LEX_MASK);
tmp |= ((clkdiv_lex[i][0] << EXYNOS5_CLKDIV_LEX_ATCLK_LEX_SHIFT) |
(clkdiv_lex[i][1] << EXYNOS5_CLKDIV_LEX_PCLK_LEX_SHIFT));
data->lex_divtable[i] = tmp;
}
tmp = __raw_readl(EXYNOS5_CLKDIV_R0X);
for (i = LV_0; i < LV_INT_END; i++) {
tmp &= ~EXYNOS5_CLKDIV_R0X_PCLK_R0X_MASK;
tmp |= (clkdiv_r0x[i][0] << EXYNOS5_CLKDIV_R0X_PCLK_R0X_SHIFT);
data->r0x_divtable[i] = tmp;
}
tmp = __raw_readl(EXYNOS5_CLKDIV_R1X);
for (i = LV_0; i < LV_INT_END; i++) {
tmp &= ~EXYNOS5_CLKDIV_R1X_PCLK_R1X_MASK;
tmp |= (clkdiv_r1x[i][0] << EXYNOS5_CLKDIV_R1X_PCLK_R1X_SHIFT);
data->r1x_divtable[i] = tmp;
}
tmp = __raw_readl(EXYNOS5_CLKDIV_CDREX);
if (samsung_rev() < EXYNOS5250_REV_1_0) {
for (i = LV_0; i < LV_MIF_END; i++) {
tmp &= ~(EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_MASK |
EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_MASK |
EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_MASK |
EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_MASK |
EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_MASK |
EXYNOS5_CLKDIV_CDREX_ACLK_CLK400_MASK |
EXYNOS5_CLKDIV_CDREX_ACLK_C2C200_MASK |
EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_MASK);
tmp |= ((clkdiv_cdrex[i][0] << EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_SHIFT) |
(clkdiv_cdrex[i][1] << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_SHIFT) |
(clkdiv_cdrex[i][2] << EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_SHIFT) |
(clkdiv_cdrex[i][3] << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_SHIFT) |
(clkdiv_cdrex[i][4] << EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_SHIFT) |
(clkdiv_cdrex[i][5] << EXYNOS5_CLKDIV_CDREX_ACLK_CLK400_SHIFT) |
(clkdiv_cdrex[i][6] << EXYNOS5_CLKDIV_CDREX_ACLK_C2C200_SHIFT) |
(clkdiv_cdrex[i][8] << EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_SHIFT));
data->cdrex_divtable[i] = tmp;
}
} else {
for (i = LV_0; i < LV_MIF_END; i++) {
tmp &= ~(EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_MASK |
EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_MASK |
EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_MASK |
EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_MASK |
EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_MASK |
EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_MASK);
tmp |= ((clkdiv_cdrex[i][0] << EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_SHIFT) |
(clkdiv_cdrex[i][1] << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_SHIFT) |
(clkdiv_cdrex[i][2] << EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_SHIFT) |
(clkdiv_cdrex[i][3] << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_SHIFT) |
(clkdiv_cdrex[i][4] << EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_SHIFT) |
(clkdiv_cdrex[i][8] << EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_SHIFT));
data->cdrex_divtable[i] = tmp;
}
}
if (samsung_rev() < EXYNOS5250_REV_1_0) {
tmp = __raw_readl(EXYNOS5_CLKDIV_CDREX2);
for (i = LV_0; i < LV_MIF_END; i++) {
tmp &= ~EXYNOS5_CLKDIV_CDREX2_MCLK_EFPHY_MASK;
tmp |= clkdiv_cdrex[i][7] << EXYNOS5_CLKDIV_CDREX2_MCLK_EFPHY_SHIFT;
data->cdrex2_divtable[i] = tmp;
}
}
exynos5250_set_bus_volt();
data->dev[PPMU_MIF] = dev;
data->dev[PPMU_INT] = &busfreq_for_int;
for (i = LV_0; i < LV_MIF_END; i++) {
ret = opp_add(data->dev[PPMU_MIF], exynos5_busfreq_table_mif[i].mem_clk,
exynos5_busfreq_table_mif[i].volt);
if (ret) {
dev_err(dev, "Fail to add opp entries.\n");
return ret;
}
}
#if defined(CONFIG_DP_60HZ_P11) || defined(CONFIG_DP_60HZ_P10)
if (cdrexfreq == 666857) {
opp_disable(data->dev[PPMU_MIF], 334000);
opp_disable(data->dev[PPMU_MIF], 110000);
} else if (cdrexfreq == 533000) {
opp_disable(data->dev[PPMU_MIF], 267000);
opp_disable(data->dev[PPMU_MIF], 107000);
} else if (cdrexfreq == 400000) {
opp_disable(data->dev[PPMU_MIF], 267000);
opp_disable(data->dev[PPMU_MIF], 100000);
}
#endif
for (i = LV_0; i < LV_INT_END; i++) {
ret = opp_add(data->dev[PPMU_INT], exynos5_busfreq_table_int[i].mem_clk,
exynos5_busfreq_table_int[i].volt);
if (ret) {
dev_err(dev, "Fail to add opp entries.\n");
return ret;
}
}
data->target = exynos5250_target;
data->get_table_index = exynos5250_get_table_index;
data->monitor = exynos5250_monitor;
data->busfreq_suspend = exynos5250_suspend;
data->busfreq_resume = exynos5250_resume;
data->sampling_rate = usecs_to_jiffies(100000);
data->table[PPMU_MIF] = exynos5_busfreq_table_mif;
data->table[PPMU_INT] = exynos5_busfreq_table_int;
/* Find max frequency for mif */
data->max_freq[PPMU_MIF] =
opp_get_freq(opp_find_freq_floor(data->dev[PPMU_MIF], &maxfreq));
data->min_freq[PPMU_MIF] =
opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_MIF], &minfreq));
data->curr_freq[PPMU_MIF] =
opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_MIF], &cdrexfreq));
/* Find max frequency for int */
maxfreq = ULONG_MAX;
minfreq = 0;
data->max_freq[PPMU_INT] =
opp_get_freq(opp_find_freq_floor(data->dev[PPMU_INT], &maxfreq));
data->min_freq[PPMU_INT] =
opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_INT], &minfreq));
data->curr_freq[PPMU_INT] =
opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_INT], &lrbusfreq));
data->vdd_reg[PPMU_INT] = regulator_get(NULL, "vdd_int");
if (IS_ERR(data->vdd_reg[PPMU_INT])) {
pr_err("failed to get resource %s\n", "vdd_int");
return -ENODEV;
}
data->vdd_reg[PPMU_MIF] = regulator_get(NULL, "vdd_mif");
if (IS_ERR(data->vdd_reg[PPMU_MIF])) {
pr_err("failed to get resource %s\n", "vdd_mif");
regulator_put(data->vdd_reg[PPMU_INT]);
return -ENODEV;
}
data->busfreq_early_suspend_handler.suspend = &busfreq_early_suspend;
data->busfreq_early_suspend_handler.resume = &busfreq_late_resume;
data->busfreq_early_suspend_handler.suspend = &busfreq_early_suspend;
data->busfreq_early_suspend_handler.resume = &busfreq_late_resume;
/* Request min 300MHz for MIF and 150MHz for INT*/
dev_lock(dev, dev, 300150);
register_early_suspend(&data->busfreq_early_suspend_handler);
tmp = __raw_readl(EXYNOS5_ABBG_INT_CONTROL);
tmp &= ~(0x1f | (1 << 31) | (1 << 7));
tmp |= ((8 + INT_RBB) | (1 << 31) | (1 << 7));
__raw_writel(tmp, EXYNOS5_ABBG_INT_CONTROL);
return 0;
}
int exynos5250_init(struct device *dev, struct busfreq_data *data)
{
unsigned int i;
unsigned long maxfreq = ULONG_MAX;
unsigned long minfreq = 0;
unsigned long cdrexfreq;
unsigned long lrbusfreq;
struct clk *clk;
int ret;
/* Enable pause function for DREX2 DVFS */
dmc_pause_ctrl = __raw_readl(EXYNOS5_DMC_PAUSE_CTRL);
dmc_pause_ctrl |= DMC_PAUSE_ENABLE;
__raw_writel(dmc_pause_ctrl, EXYNOS5_DMC_PAUSE_CTRL);
clk = clk_get(NULL, "mout_cdrex");
if (IS_ERR(clk)) {
dev_err(dev, "Fail to get mclk_cdrex clock");
ret = PTR_ERR(clk);
return ret;
}
cdrexfreq = clk_get_rate(clk) / 1000;
clk_put(clk);
clk = clk_get(NULL, "aclk_266");
if (IS_ERR(clk)) {
dev_err(dev, "Fail to get aclk_266 clock");
ret = PTR_ERR(clk);
return ret;
}
lrbusfreq = clk_get_rate(clk) / 1000;
clk_put(clk);
if (cdrexfreq == 800000) {
clkdiv_cdrex = clkdiv_cdrex_for800;
exynos5_busfreq_table_mif = exynos5_busfreq_table_for800;
exynos5_mif_volt = exynos5_mif_volt_for800;
} else if (cdrexfreq == 666857) {
clkdiv_cdrex = clkdiv_cdrex_for667;
exynos5_busfreq_table_mif = exynos5_busfreq_table_for667;
exynos5_mif_volt = exynos5_mif_volt_for667;
} else if (cdrexfreq == 533000) {
clkdiv_cdrex = clkdiv_cdrex_for533;
exynos5_busfreq_table_mif = exynos5_busfreq_table_for533;
exynos5_mif_volt = exynos5_mif_volt_for533;
} else if (cdrexfreq == 400000) {
clkdiv_cdrex = clkdiv_cdrex_for400;
exynos5_busfreq_table_mif = exynos5_busfreq_table_for400;
exynos5_mif_volt = exynos5_mif_volt_for400;
} else {
dev_err(dev, "Don't support cdrex table\n");
return -EINVAL;
}
exynos5250_set_bus_volt();
data->dev[PPMU_MIF] = dev;
data->dev[PPMU_INT] = &busfreq_for_int;
for (i = LV_0; i < LV_MIF_END; i++) {
ret = opp_add(data->dev[PPMU_MIF], exynos5_busfreq_table_mif[i].mem_clk,
exynos5_busfreq_table_mif[i].volt);
if (ret) {
dev_err(dev, "Fail to add opp entries.\n");
return ret;
}
}
opp_disable(data->dev[PPMU_MIF], 107000);
for (i = LV_0; i < LV_INT_END; i++) {
ret = opp_add(data->dev[PPMU_INT], exynos5_busfreq_table_int[i].mem_clk,
exynos5_busfreq_table_int[i].volt);
if (ret) {
dev_err(dev, "Fail to add opp entries.\n");
return ret;
}
}
data->target = exynos5250_target;
data->get_table_index = exynos5250_get_table_index;
data->monitor = exynos5250_monitor;
data->busfreq_suspend = exynos5250_suspend;
data->busfreq_resume = exynos5250_resume;
data->sampling_rate = usecs_to_jiffies(100000);
data->table[PPMU_MIF] = exynos5_busfreq_table_mif;
data->table[PPMU_INT] = exynos5_busfreq_table_int;
/* Find max frequency for mif */
data->max_freq[PPMU_MIF] =
opp_get_freq(opp_find_freq_floor(data->dev[PPMU_MIF], &maxfreq));
data->min_freq[PPMU_MIF] =
opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_MIF], &minfreq));
data->curr_freq[PPMU_MIF] =
opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_MIF], &cdrexfreq));
/* Find max frequency for int */
maxfreq = ULONG_MAX;
minfreq = 0;
data->max_freq[PPMU_INT] =
opp_get_freq(opp_find_freq_floor(data->dev[PPMU_INT], &maxfreq));
data->min_freq[PPMU_INT] =
opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_INT], &minfreq));
data->curr_freq[PPMU_INT] =
opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_INT], &lrbusfreq));
data->vdd_reg[PPMU_INT] = regulator_get(NULL, "vdd_int");
if (IS_ERR(data->vdd_reg[PPMU_INT])) {
pr_err("failed to get resource %s\n", "vdd_int");
return -ENODEV;
}
data->vdd_reg[PPMU_MIF] = regulator_get(NULL, "vdd_mif");
if (IS_ERR(data->vdd_reg[PPMU_MIF])) {
pr_err("failed to get resource %s\n", "vdd_mif");
regulator_put(data->vdd_reg[PPMU_INT]);
return -ENODEV;
}
data->busfreq_early_suspend_handler.suspend = &busfreq_early_suspend;
data->busfreq_early_suspend_handler.resume = &busfreq_late_resume;
/* Request min 300MHz */
dev_lock(dev, dev, 300000);
register_early_suspend(&data->busfreq_early_suspend_handler);
tmp = __raw_readl(EXYNOS5_ABBG_INT_CONTROL);
tmp &= ~(0x1f | (1 << 31) | (1 << 7));
tmp |= ((8 + INT_RBB) | (1 << 31) | (1 << 7));
__raw_writel(tmp, EXYNOS5_ABBG_INT_CONTROL);
return 0;
}
