// Create tasks.
void os_create_tasks(void)
{
os_create_idle(
os_default_idle,
0x0, /*pdata*/
512 /*in sizeof(C64_STACK) 8bit*/
);
os_create_task(OS_TSK_PRITASK, /*task type*/
appBackground, /*task entry function*/
0x0, /*pdata*/
t_dsp_appBackground_ID, /*task id*/
4096, /*in sizeof(C64_STACK) 8bit*/
24, /*priority*/
NULLVECTOR); /*interrupt pin*/
#if 0
os_create_task(OS_TSK_PRITASK, /*task type*/
t_dsp_check_io, /*task entry function*/
0x0, /*pdata*/
t_dsp_check_io_ID, /*task id*/
4096, /*in sizeof(C64_STACK) 8bit*/
24, /*priority*/
NULLVECTOR); /*interrupt pin*/
os_create_task(OS_TSK_PRITASK, /*task type*/
t_dsp_send, /*task entry function*/
0x0, /*pdata*/
t_dsp_send_ID, /*task id*/
4096, /*in sizeof(C64_STACK) 8bit*/
20, /*priority*/
NULLVECTOR); /*interrupt pin*/
#endif
}
os_status osHwiCreate(os_hwi_handle hwi_num,
os_hwi_priority priority,
os_hwi_mode mode,
os_hwi_function handler,
os_hwi_arg argument)
{
uint16_t index;
uint32_t mode_bit;
uint32_t *trigger_reg_ptr;
uint32_t trigger_reg;
/* handle the mode register ELRx */
index = (uint16_t)((hwi_num - 18) >> 5);
trigger_reg_ptr = (uint32_t *)((g_dsp_plat_map->epic).p_elr);
trigger_reg_ptr += index;
mode_bit = (uint32_t)(0x00000001 << ((hwi_num - 18) & 0x001F));
if (mode == LEVEL_MODE)
{
READ_UINT32(trigger_reg, *trigger_reg_ptr);
trigger_reg &= ~mode_bit;
WRITE_UINT32(*trigger_reg_ptr, trigger_reg);
}
else if(mode == EDGE_MODE)
{
READ_UINT32(trigger_reg, *trigger_reg_ptr);
trigger_reg |= mode_bit;
WRITE_UINT32(*trigger_reg_ptr, trigger_reg);
}
/* create hwi task using phoenix API */
(void)os_create_task(PHOENIX_TSK_INTTASK,
(PHOENIX_TSKFUNC)handler,
0,
hwi_num,
0,
priority,
(PHOENIX_INTVECTOR)(hwi_num - 18));
/* Store handler into table */
interrupt_pointer[hwi_num] = handler;
if (hwi_num == OS_INT_ORED_GENERAL)
interrupt_argument[hwi_num] = (os_hwi_arg)general_ored_interrupt;
else if (hwi_num == OS_INT_ORED_DEBUG)
interrupt_argument[hwi_num] = (os_hwi_arg)debug_ored_interrupt;
else if (hwi_num == OS_INT_ORED_MAPLE)
interrupt_argument[hwi_num] = (os_hwi_arg)maple_ored_interrupt;
else
interrupt_argument[hwi_num] = argument;
return OS_SUCCESS;
#if 0
os_status status = OS_SUCCESS;
os_hwi_status int_status;
uint16_t index;
uint32_t pending_bit, mode_bit;
uint32_t *pending_reg_ptr, *trigger_reg_ptr;
uint32_t trigger_reg;
os_hwi_handle epic_hwi_num = 0;
#ifdef HWI_ERROR_CHECKING
if ( (priority > OS_HWI_LAST_PRIORITY) && (priority != OS_HWI_PRIORITY_NMI) )
{
#ifdef HWI_ERROR_ASSERT
OS_ASSERT;
#endif /* HWI_ERROR_ASSERT */
RETURN_ERROR(OS_ERR_HWI_PRIORITY_INVALID);
}
if (handler == NULL)
{
#ifdef HWI_ERROR_ASSERT
OS_ASSERT;
#endif /* HWI_ERROR_ASSERT */
RETURN_ERROR(OS_ERR_HWI_FUNCTION_INVALID);
}
if (HWI_INVALID_MODE(mode))
{
#ifdef HWI_ERROR_ASSERT
OS_ASSERT;
#endif /* HWI_ERROR_ASSERT */
if(priority != 0) //meaning disable only
{
RETURN_ERROR(OS_ERR_HWI_MODE_INVALID);
}
}
#endif /* HWI_ERROR_CHECKING */
if (hwi_num > OS_INT_LAST)
{
if(hwi_num > OS_INT_GEN_LAST)
{
#ifdef HWI_ERROR_ASSERT
OS_ASSERT;
#endif /* HWI_ERROR_ASSERT */
RETURN_ERROR(OS_ERR_HWI_INVALID);
}
else
{
return osHwiCreateGeneral(hwi_num,handler,argument);
}
}
if ( (priority > 0) && (priority != OS_HWI_PRIORITY_NMI) )
priority = (os_hwi_priority)((OS_HWI_LAST_PRIORITY + 1) - priority);
int_status = osHwiDisable();
#ifdef HWI_LOGGING
if (priority != OS_HWI_PRIORITY_NMI)
osLog(LOG_HWI_CREATE, (uint32_t)(((OS_HWI_LAST_PRIORITY - priority)<<16) | (hwi_num)));
else
osLog(LOG_HWI_CREATE, (uint32_t)(((0xFFFF)<<16) | (hwi_num))); /* for NMI interrupts */
#endif
/* Store handler into table */
interrupt_pointer[hwi_num] = handler;
if (hwi_num == OS_INT_ORED_GENERAL)
interrupt_argument[hwi_num] = (os_hwi_arg)general_ored_interrupt;
else if (hwi_num == OS_INT_ORED_DEBUG)
interrupt_argument[hwi_num] = (os_hwi_arg)debug_ored_interrupt;
else if (hwi_num == OS_INT_ORED_MAPLE)
interrupt_argument[hwi_num] = (os_hwi_arg)maple_ored_interrupt;
else
interrupt_argument[hwi_num] = argument;
/* Non-EPIC interrupts don't require any more handling */
if (hwi_num < EPIC_INTERRUPTS_OFFSET)
{
osHwiEnable(int_status);
return status;
}
else /* get the EPIC interrupt zero-based index */
epic_hwi_num = (os_hwi_handle)(hwi_num - EPIC_INTERRUPTS_OFFSET);
prioritySet(epic_hwi_num, priority);
/* handle the mode register ELRx */
index = (uint16_t)(epic_hwi_num >> 5); /* /32 */
trigger_reg_ptr = (uint32_t *)((g_dsp_plat_map->epic).p_elr);
trigger_reg_ptr += index;
mode_bit = (uint32_t)(0x00000001 << (epic_hwi_num & 0x001F));
if (mode == LEVEL_MODE)
{
READ_UINT32(trigger_reg, *trigger_reg_ptr);
trigger_reg &= ~mode_bit;
WRITE_UINT32(*trigger_reg_ptr, trigger_reg);
}
else // mode == EDGE_MODE
{
READ_UINT32(trigger_reg, *trigger_reg_ptr);
trigger_reg |= mode_bit;
WRITE_UINT32(*trigger_reg_ptr, trigger_reg);
}
/* handle the pending interrupt register */
index = (uint16_t)(epic_hwi_num >> 5); /* /32 */
pending_reg_ptr = (uint32_t *)((g_dsp_plat_map->epic).p_ipr);
pending_reg_ptr += index;
/* Figure out what the pending mask looks like */
pending_bit = (uint32_t)(0x00000001 << (epic_hwi_num & 0x001F));
/* Clear any pending interrupts */
WRITE_UINT32(*pending_reg_ptr,pending_bit);
/* enable the interrupt in the ENDIS register */
setInterruptEnable(hwi_num, TRUE);
osHwiEnable(int_status);
return status;
#endif
}
/*---------------------------------------------------------------------------------------------------------*/
uint8_t sw_uart_wrapper_ioctl(void * const aHandle ,const uint8_t aIoctl_num , void * aIoctl_param1 , void * aIoctl_param2)
{
rx_int_size_t WritePos,ReadPos;
#if SW_UART_WRAPPER_CONFIG_MAX_RX_BUFFER_SIZE>0
WritePos=INSTANCE(aHandle)->WritePos;
ReadPos=INSTANCE(aHandle)->ReadPos;
#endif
switch(aIoctl_num)
{
#if SW_UART_WRAPPER_CONFIG_NUM_OF_DYNAMIC_INSTANCES > 0
case IOCTL_GET_PARAMS_ARRAY_FUNC :
*(const dev_param_t**)aIoctl_param1 = SW_UART_WRAPPER_Dev_Params;
*(uint8_t*)aIoctl_param2 = sizeof(SW_UART_WRAPPER_Dev_Params)/sizeof(dev_param_t); //size
break;
case IOCTL_SET_SERVER_DEVICE :
INSTANCE(aHandle)->server_dev = DEV_OPEN((uint8_t*)aIoctl_param1);
if (NULL!=INSTANCE(aHandle)->server_dev)
{
DEV_IOCTL(INSTANCE(aHandle)->server_dev,IOCTL_SET_ISR_CALLBACK_DEV, (void*)INSTANCE(aHandle)->this_dev);
}
break;
#if SW_UART_WRAPPER_CONFIG_MAX_RX_BUFFER_SIZE>0
case IOCTL_SW_UART_WRAPPER_SET_BUFF_SIZE :
INSTANCE(aHandle)->rx_buff_size = atoi((char*)aIoctl_param1);
INSTANCE(aHandle)->rx_buff = (uint8_t*)malloc(INSTANCE(aHandle)->rx_buff_size);
break;
case IOCTL_SET_ISR_CALLBACK_DEV :
INSTANCE(aHandle)->client_dev = (pdev_descriptor)aIoctl_param1;
break;
#endif //for SW_UART_WRAPPER_CONFIG_MAX_RX_BUFFER_SIZE>0
#endif // for SW_UART_WRAPPER_CONFIG_NUM_OF_DYNAMIC_INSTANCES > 0
#if SW_UART_WRAPPER_CONFIG_MAX_RX_BUFFER_SIZE>0
case IOCTL_GET_AND_LOCK_DATA_BUFFER :
INSTANCE(aHandle)->isDataInUse=1; // should be modified first
((ioctl_get_data_buffer_t *)aIoctl_param1)->bufferWasOverflowed = INSTANCE(aHandle)->bufferWasOverflowed ;
INSTANCE(aHandle)->bufferWasOverflowed = 0;
((ioctl_get_data_buffer_t *)aIoctl_param1)->TotalLength = WritePos - ReadPos;
((ioctl_get_data_buffer_t *)aIoctl_param1)->pBufferStart = &INSTANCE(aHandle)->rx_buff[ReadPos];
break;
case IOCTL_SET_BYTES_CONSUMED_IN_DATA_BUFFER :
INSTANCE(aHandle)->ReadPos += (size_t)aIoctl_param1;
if( ReadPos > WritePos)
{
// should not be reached :
INSTANCE(aHandle)->ReadPos = WritePos;
}
break;
case IOCTL_SET_UNLOCK_DATA_BUFFER :
INSTANCE(aHandle)->isDataInUse= 0 ; // should be modified last
break;
#endif // for SW_UART_WRAPPER_CONFIG_MAX_RX_BUFFER_SIZE>0
case IOCTL_SW_UART_WRAPPER_RESET :
DEV_IOCTL_0_PARAMS(INSTANCE(aHandle)->server_dev,IOCTL_UART_DISABLE_TX);
break;
case IOCTL_SW_UART_WRAPPER_USE_TASK :
INSTANCE(aHandle)->use_task_for_out = (size_t)aIoctl_param1;
break;
case IOCTL_DEVICE_START :
os_create_task("sw_uart_wrapper_task",SW_UART_WRAPPER_Send_Task,
aHandle , SW_UART_WRAPPER_CONFIG_TASK_STACK_SIZE , SW_UART_WRAPPER_CONFIG_TASK_PRIORITY);
break;
default :
return 1;
}
return 0;
}
