void machine_kexec(struct kimage *image) { unsigned long page_list; unsigned long reboot_code_buffer_phys; void *reboot_code_buffer; arch_kexec(); page_list = image->head & PAGE_MASK; /* we need both effective and real address here */ reboot_code_buffer_phys = page_to_pfn(image->control_code_page) << PAGE_SHIFT; reboot_code_buffer = page_address(image->control_code_page); /* Prepare parameters for reboot_code_buffer*/ mem_text_write_kernel_word(&kexec_start_address, image->start); mem_text_write_kernel_word(&kexec_indirection_page, page_list); mem_text_write_kernel_word(&kexec_mach_type, machine_arch_type); mem_text_write_kernel_word(&kexec_boot_atags, image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET); #ifdef CONFIG_KEXEC_HARDBOOT mem_text_write_kernel_word(&kexec_hardboot, image->hardboot); #endif /* copy our kernel relocation code to the control code page */ memcpy(reboot_code_buffer, relocate_new_kernel, relocate_new_kernel_size); flush_icache_range((unsigned long) reboot_code_buffer, (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); printk(KERN_INFO "Bye!\n"); if (kexec_reinit) kexec_reinit(); local_irq_disable(); local_fiq_disable(); setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/ #ifdef CONFIG_KEXEC_HARDBOOT if (image->hardboot && kexec_hardboot_hook) /* Run any final machine-specific shutdown code. */ kexec_hardboot_hook(); #endif flush_cache_all(); outer_flush_all(); outer_disable(); cpu_proc_fin(); outer_inv_all(); flush_cache_all(); __virt_to_phys(cpu_reset)(reboot_code_buffer_phys); }
void hi6930_pm_enable_l2x0(void) { u32 l2x0_base = HI_APPA9_L2_REGBASE_ADDR_VIRT; /* disable cache */ writel_relaxed(0, l2x0_base + L2X0_CTRL); /* restore aux control register */ writel_relaxed(l2x0_cache_bak[0], l2x0_base + L2X0_AUX_CTRL); writel_relaxed(l2x0_cache_bak[1], l2x0_base + L2X0_TAG_LATENCY_CTRL); writel_relaxed(l2x0_cache_bak[2], l2x0_base + L2X0_DATA_LATENCY_CTRL); /* invalidate l2x0 cache */ outer_inv_all(); /* enable l2x0 cache */ writel_relaxed(1, l2x0_base + L2X0_CTRL); mb(); pm_printk(BSP_LOG_LEVEL_DEBUG, "L2 Cache enabled\r\n"); }
void machine_kexec(struct kimage *image) { unsigned long page_list; unsigned long reboot_code_buffer_phys; void *reboot_code_buffer; if (num_online_cpus() > 1) { pr_err("kexec: error: multiple CPUs still online\n"); return; } page_list = image->head & PAGE_MASK; /* we need both effective and real address here */ reboot_code_buffer_phys = page_to_pfn(image->control_code_page) << PAGE_SHIFT; reboot_code_buffer = page_address(image->control_code_page); /* Prepare parameters for reboot_code_buffer*/ kexec_start_address = image->start; kexec_indirection_page = page_list; kexec_mach_type = machine_arch_type; kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET; /* copy our kernel relocation code to the control code page */ memcpy(reboot_code_buffer, relocate_new_kernel, relocate_new_kernel_size); flush_icache_range((unsigned long) reboot_code_buffer, (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); printk(KERN_INFO "Bye!\n"); if (kexec_reinit) kexec_reinit(); local_irq_disable(); local_fiq_disable(); setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/ flush_cache_all(); outer_flush_all(); outer_disable(); cpu_proc_fin(); outer_inv_all(); flush_cache_all(); cpu_reset(reboot_code_buffer_phys); }
s32_t pwrctrl_l2c_enable( void_t ) { #ifdef CONFIG_CACHE_L2X0 #ifdef CHIP_BB_HI6210 /*no need*/ #else /* invalidate l2x0 cache */ /* l2x0_inv_all();*/ outer_inv_all(); /* enable l2x0 cache */ pwrctrl_write_reg32(ACPU_L2CC_CTRL_VA,PWRCTRL_SWITCH_ON); mb(); #endif #endif return RET_OK; }
void machine_kexec(struct kimage *image) { unsigned long page_list; unsigned long reboot_code_buffer_phys; void *reboot_code_buffer; page_list = image->head & PAGE_MASK; /* we need both effective and real address here */ reboot_code_buffer_phys = page_to_pfn(image->control_code_page) << PAGE_SHIFT; reboot_code_buffer = page_address(image->control_code_page); /* Prepare parameters for reboot_code_buffer*/ kexec_start_address = image->start; kexec_indirection_page = page_list; kexec_mach_type = machine_arch_type; kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET; /* copy our kernel relocation code to the control code page */ memcpy(reboot_code_buffer, relocate_new_kernel, relocate_new_kernel_size); flush_icache_range((unsigned long) reboot_code_buffer, (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); printk(KERN_INFO "Bye!\n"); outer_flush_all(); outer_disable(); local_irq_disable(); local_fiq_disable(); outer_inv_all(); flush_cache_all(); cpu_proc_fin(); flush_cache_all(); __virt_to_phys(cpu_reset)(reboot_code_buffer_phys); }
static void exynos4_pm_resume(void) { unsigned long tmp; void __iomem *inform1; /* If PMU failed while entering sleep mode, WFI will be * ignored by PMU and then exiting cpu_do_idle(). * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically * in this situation. */ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { tmp |= S5P_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); /* No need to perform below restore code */ pr_info("%s: early_wakeup\n", __func__); goto early_wakeup; } /* For release retention */ __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); s3c_pm_do_restore(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save)); if (soc_is_exynos4210()) s3c_pm_do_restore(exynos4210_regs_save, ARRAY_SIZE(exynos4210_regs_save)); else s3c_pm_do_restore(exynos4x12_regs_save, ARRAY_SIZE(exynos4x12_regs_save)); if (!exynos4_is_c2c_use()) s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); else { if (!soc_is_exynos4210()) { /* Gating CLK_SSS */ tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC); tmp &= ~(0x1 << 4); __raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC); } } tmp = __raw_readl(S5P_WAKEUP_STAT); if (WARN_ON(!tmp) && soc_is_exynos4412()) { __raw_writel(__raw_readl(S5P_EINT_PEND(0)), S5P_EINT_PEND(0)); __raw_writel(__raw_readl(S5P_EINT_PEND(1)), S5P_EINT_PEND(1)); __raw_writel(__raw_readl(S5P_EINT_PEND(2)), S5P_EINT_PEND(2)); __raw_writel(__raw_readl(S5P_EINT_PEND(3)), S5P_EINT_PEND(3)); __raw_writel(0x01010001, S5P_ARM_CORE_OPTION(0)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(1)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(2)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(3)); } #ifdef CONFIG_HAVE_ARM_SCU scu_enable(S5P_VA_SCU); #endif #ifdef CONFIG_CACHE_L2X0 if (trustzone_on()) { /* * Restore for Outer cache */ exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val, exynos4_l2cc_save[1].val, exynos4_l2cc_save[2].val); exynos_smc(SMC_CMD_L2X0SETUP2, L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, 0x7C470001, 0xC200FFFF); exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); } else { s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); outer_inv_all(); /* enable L2X0*/ writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); } #endif early_wakeup: if (!soc_is_exynos4210()) exynos4_reset_assert_ctrl(1); #ifdef CONFIG_CACHE_L2X0 /* Enable the full line of zero */ enable_cache_foz(); #endif if (trustzone_on()) { inform1 = S5P_VA_SYSRAM_NS + 0xC; } else { inform1 = S5P_INFORM1; } /* Clear Check mode */ __raw_writel(0x0, inform1); return; }
static void exynos4_pm_resume(void) { unsigned long tmp; /* If PMU failed while entering sleep mode, WFI will be * ignored by PMU and then exiting cpu_do_idle(). * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically * in this situation. */ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { tmp |= S5P_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); /* No need to perform below restore code */ pr_info("%s: early_wakeup\n", __func__); goto early_wakeup; } /* For release retention */ __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); s3c_pm_do_restore(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save)); if (soc_is_exynos4210()) s3c_pm_do_restore(exynos4210_regs_save, ARRAY_SIZE(exynos4210_regs_save)); else s3c_pm_do_restore(exynos4x12_regs_save, ARRAY_SIZE(exynos4x12_regs_save)); #if defined(CONFIG_MACH_M0_CTC) { if (max7693_muic_cp_usb_state()) { if (system_rev < 11) { gpio_direction_output(GPIO_USB_BOOT_EN, 1); } else if (system_rev == 11) { gpio_direction_output(GPIO_USB_BOOT_EN, 1); gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1); } else { gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1); } } } #endif CHECK_POINT; if (!exynos4_is_c2c_use()) s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); else { if (!soc_is_exynos4210()) { /* Gating CLK_SSS */ tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC); tmp &= ~(0x1 << 4); __raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC); } } /* For the suspend-again to check the value */ s3c_suspend_wakeup_stat = __raw_readl(S5P_WAKEUP_STAT); CHECK_POINT; scu_enable(S5P_VA_SCU); CHECK_POINT; #ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_ARM_TRUSTZONE /* * Restore for Outer cache */ exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val, exynos4_l2cc_save[1].val, exynos4_l2cc_save[2].val); CHECK_POINT; exynos_smc(SMC_CMD_L2X0SETUP2, L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, 0x7C470001, 0xC200FFFF); CHECK_POINT; exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); CHECK_POINT; exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); #else s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); outer_inv_all(); /* enable L2X0*/ writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); #endif /* Enable the full line of zero */ enable_cache_foz(); #endif CHECK_POINT; early_wakeup: if (!soc_is_exynos4210()) exynos4_reset_assert_ctrl(1); CHECK_POINT; /* Clear Check mode */ __raw_writel(0x0, REG_INFORM1); return; }
static void exynos4_pm_resume(void) { unsigned long tmp; /* If PMU failed while entering sleep mode, WFI will be * ignored by PMU and then exiting cpu_do_idle(). * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically * in this situation. */ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { tmp |= S5P_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); /* No need to perform below restore code */ goto early_wakeup; } /* For release retention */ __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); if (!exynos4_is_c2c_use()) s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); else { if (!soc_is_exynos4210()) { /* Gating CLK_SSS */ tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC); tmp &= ~(0x1 << 4); __raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC); } } exynos4_scu_enable(S5P_VA_SCU); #ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_ARM_TRUSTZONE /* * Restore for Outer cache */ exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val, exynos4_l2cc_save[1].val, exynos4_l2cc_save[2].val); exynos_smc(SMC_CMD_L2X0SETUP2, L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, 0x7C470001, 0xC200FFFF); exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); #else s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); outer_inv_all(); /* enable L2X0*/ writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); #endif #endif early_wakeup: if (!soc_is_exynos4210()) exynos4_reset_assert_ctrl(1); #ifdef CONFIG_CACHE_L2X0 /* Enable the full line of zero */ enable_cache_foz(); #endif /* Clear Check mode */ __raw_writel(0x0, REG_INFORM1); return; }