void OVLClockOn(DISP_MODULE_ENUM module,void * handle)
{
int idx = ovl_index(module);
ddp_enable_module_clock(module);
DDPMSG("OVL%dClockOn CG 0x%x \n",idx, DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0));
return;
}
static void ovl_store_regs(DISP_MODULE_ENUM module)
{
int i = 0;
int idx = ovl_index(module);
unsigned int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
#if 0
static const unsigned long regs[] = {
DISP_REG_OVL_ROI_SIZE, DISP_REG_OVL_ROI_BGCLR,
};
#else
static unsigned long regs[3];
regs[0] = DISP_REG_OVL_ROI_SIZE + idx_offset;
regs[1] = DISP_REG_OVL_ROI_BGCLR + idx_offset;
regs[2] = DISP_REG_OVL_DATAPATH_CON + idx_offset;
#endif
reg_back_cnt[idx] = sizeof(regs)/sizeof(unsigned long);
ASSERT(reg_back_cnt[idx] <= OVL_REG_BACK_MAX);
for (i = 0; i < reg_back_cnt[idx]; i++) {
reg_back[idx][i].address = regs[i];
reg_back[idx][i].value = DISP_REG_GET(regs[i]);
}
DDPMSG("store %d cnt registers on ovl %d\n", reg_back_cnt[idx], idx);
}
int OVLLayerSwitch(DISP_MODULE_ENUM module,
unsigned layer,
unsigned int en,
void * handle)
{
int idx = ovl_index(module);
ASSERT(layer<=3);
switch(layer) {
case 0:
DISP_REG_SET_FIELD(handle,SRC_CON_FLD_L0_EN, idx*DISP_INDEX_OFFSET+DISP_REG_OVL_SRC_CON, en);
break;
case 1:
DISP_REG_SET_FIELD(handle,SRC_CON_FLD_L1_EN, idx*DISP_INDEX_OFFSET+DISP_REG_OVL_SRC_CON, en);
break;
case 2:
DISP_REG_SET_FIELD(handle,SRC_CON_FLD_L2_EN, idx*DISP_INDEX_OFFSET+DISP_REG_OVL_SRC_CON, en);
break;
case 3:
DISP_REG_SET_FIELD(handle,SRC_CON_FLD_L3_EN, idx*DISP_INDEX_OFFSET+DISP_REG_OVL_SRC_CON, en);
break;
default:
DDPERR("invalid layer=%d\n", layer); // invalid layer
ASSERT(0);
}
return 0;
}
int ovl_layer_switch(DISP_MODULE_ENUM module,
unsigned layer,
unsigned int en,
void *handle)
{
int idx = ovl_index(module);
int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
ASSERT(layer <= 3);
// DDPDBG("ovl%d,layer %d,enable %d\n", idx, layer, en);
switch (layer) {
case 0:
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_RDMA0_CTRL, en);
break;
case 1:
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_RDMA1_CTRL, en);
break;
case 2:
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_RDMA2_CTRL, en);
break;
case 3:
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_RDMA3_CTRL, en);
break;
default:
DDPERR("invalid layer=%d\n", layer);
ASSERT(0);
}
return 0;
}
void OVLDeInit(DISP_MODULE_ENUM module,void * handle)
{
int idx = ovl_index(module);
DDPMSG("OVL%dDeInit close CG \n",idx);
ddp_disable_module_clock(module);
return;
}
int ovl_start(DISP_MODULE_ENUM module, void *handle)
{
int idx = ovl_index(module);
int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_EN, 0x01);
int enable_ovl_irq = 1;
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
enable_ovl_irq = 1;
#else
if(gEnableIRQ==1)
enable_ovl_irq = 1;
else
enable_ovl_irq = 0;
#endif
if(enable_ovl_irq)
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_INTEN, 0x1e2);
else
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_INTEN, 0x1e0);
DISP_REG_SET_FIELD(handle, DATAPATH_CON_FLD_LAYER_SMI_ID_EN,
idx_offset+DISP_REG_OVL_DATAPATH_CON, 0x1);
return 0;
}
int OVLStop(DISP_MODULE_ENUM module,void * handle) {
int idx = ovl_index(module);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_INTEN, 0x00);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_EN, 0x00);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_INTSTA, 0x00);
return 0;
}
void OVLInit(DISP_MODULE_ENUM module,void * handle)
{
//power on, no need to care clock
int idx = ovl_index(module);
ddp_enable_module_clock(module);
DDPMSG("OVL%dInit open CG 0x%x \n",idx, DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0));
return;
}
int OVLStart(DISP_MODULE_ENUM module,void * handle) {
int idx = ovl_index(module);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_INTEN, 0x0E);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_EN, 0x01);
DISP_REG_SET_FIELD(handle,DATAPATH_CON_FLD_LAYER_SMI_ID_EN,
idx*DISP_INDEX_OFFSET+DISP_REG_OVL_DATAPATH_CON,0x1);
return 0;
}
int ovl_is_idle(DISP_MODULE_ENUM module)
{
int idx = ovl_index(module);
int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
if(((DISP_REG_GET(idx_offset+DISP_REG_OVL_FLOW_CTRL_DBG)&0x3ff)!=0x1) &&
((DISP_REG_GET(idx_offset+DISP_REG_OVL_FLOW_CTRL_DBG)&0x3ff)!=0x2))
{return 0;}
else
{return 1;}
}
int ovl_stop(DISP_MODULE_ENUM module, void *handle)
{
int idx = ovl_index(module);
int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_INTEN, 0x00);
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_EN, 0x00);
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_INTSTA, 0x00);
return 0;
}
int ovl_resume(DISP_MODULE_ENUM module, void *handle)
{
int idx = ovl_index(module);
DDPMSG("ovl%d_resume\n", idx);
#ifdef ENABLE_CLK_MGR
if(idx == 0){
enable_clock(MT_CG_DISP0_DISP_OVL0, "OVL0");
}
#endif
ovl_restore_regs(module, handle);
return 0;
}
void OVLRegRestore(DISP_MODULE_ENUM module,void * handle)
{
int idx = ovl_index(module);
int i = reg_back_cnt[idx];
while(i > 0)
{
i--;
DISP_REG_SET(handle,reg_back[idx][i].address, reg_back[idx][i].value);
}
DDPDBG("restore %d cnt registers on ovl %d",reg_back_cnt[idx],idx);
reg_back_cnt[idx] = 0;
}
int ovl_clock_on(DISP_MODULE_ENUM module, void *handle)
{
int idx = ovl_index(module);
DDPMSG("ovl%d_clock_on\n", idx);
#ifdef ENABLE_CLK_MGR
if(idx == 0){
enable_clock(MT_CG_DISP0_DISP_OVL0, "OVL0");
}
ovl_clock_cnt[idx]++;
#endif
return 0;
}
void OVLClockOff(DISP_MODULE_ENUM module,void * handle)
{
int idx = ovl_index(module);
DDPMSG("OVL%dClockOff\n",idx);
//store registers
// OVLRegRestore(module,handle);
DISP_REG_SET(handle, idx * DISP_INDEX_OFFSET + DISP_REG_OVL_EN, 0x00);
OVLReset(module,handle);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_INTEN, 0x00);
DISP_REG_SET(handle, idx * DISP_INDEX_OFFSET + DISP_REG_OVL_INTSTA, 0x00);
ddp_disable_module_clock(module);
return;
}
int ovl_suspend(DISP_MODULE_ENUM module, void *handle)
{
int idx = ovl_index(module);
DDPMSG("ovl%d_suspend\n", idx);
ovl_store_regs(module);
#ifdef ENABLE_CLK_MGR
if(idx == 0){
disable_clock(MT_CG_DISP0_DISP_OVL0+idx, "OVL0");
}else{
disable_clock(MT_CG_DISP0_DISP_OVL0+idx, "OVL1");
}
#endif
return 0;
}
void ovl_get_address(DISP_MODULE_ENUM module, unsigned long *add)
{
int i = 0;
int idx = ovl_index(module);
unsigned int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
unsigned int layer_off = 0;
unsigned int src_on = DISP_REG_GET(DISP_REG_OVL_SRC_CON + idx_offset);
for (i = 0; i < 4; i++) {
layer_off = i*OVL_LAYER_OFFSET + idx_offset;
if (src_on & (0x1<<i)) {
add[i] = DISP_REG_GET(layer_off+DISP_REG_OVL_L0_ADDR);
}else{
add[i] = 0;
}
}
return;
}
int ovl_roi(DISP_MODULE_ENUM module,
unsigned int bg_w, unsigned int bg_h, unsigned int bg_color, void *handle)
{
int idx = ovl_index(module);
int idx_offset = idx * DISP_OVL_INDEX_OFFSET;
if ((bg_w > OVL_MAX_WIDTH) || (bg_h > OVL_MAX_HEIGHT)) {
DDPERR("ovl_roi,exceed OVL max size, w=%d, h=%d\n", bg_w, bg_h);
ASSERT(0);
}
DISP_REG_SET(handle, idx_offset + DISP_REG_OVL_ROI_SIZE, bg_h << 16 | bg_w);
DISP_REG_SET(handle, idx_offset + DISP_REG_OVL_ROI_BGCLR, bg_color);
return 0;
}
int OVLReset(DISP_MODULE_ENUM module,void * handle) {
#define OVL_IDLE (0x3)
unsigned int delay_cnt = 0;
int idx = ovl_index(module);
/*always use cpu do reset*/
DISP_CPU_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_OVL_RST, 0x1); // soft reset
DISP_CPU_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_OVL_RST, 0x0);
while(!(DISP_REG_GET(idx*DISP_INDEX_OFFSET+DISP_REG_OVL_FLOW_CTRL_DBG) & OVL_IDLE))
{
delay_cnt++;
udelay(10);
if(delay_cnt>2000)
{
DDPERR("OVL%dReset() timeout! \n",idx);
break;
}
}
return 0;
}
void OVLRegStore(DISP_MODULE_ENUM module)
{
int i =0;
int idx = ovl_index(module);
static const unsigned int regs[] =
{
//start
DISP_REG_OVL_INTEN , DISP_REG_OVL_EN ,DISP_REG_OVL_DATAPATH_CON,
// roi
DISP_REG_OVL_ROI_SIZE , DISP_REG_OVL_ROI_BGCLR ,
//layers enable
DISP_REG_OVL_SRC_CON,
//layer0
DISP_REG_OVL_RDMA0_CTRL , DISP_REG_OVL_L0_CON ,DISP_REG_OVL_L0_SRC_SIZE,
DISP_REG_OVL_L0_OFFSET , DISP_REG_OVL_L0_ADDR ,DISP_REG_OVL_L0_PITCH,
DISP_REG_OVL_L0_SRCKEY ,
//layer1
DISP_REG_OVL_RDMA1_CTRL , DISP_REG_OVL_L1_CON ,DISP_REG_OVL_L1_SRC_SIZE,
DISP_REG_OVL_L1_OFFSET , DISP_REG_OVL_L1_ADDR ,DISP_REG_OVL_L1_PITCH,
DISP_REG_OVL_L1_SRCKEY ,
//layer2
DISP_REG_OVL_RDMA2_CTRL , DISP_REG_OVL_L2_CON ,DISP_REG_OVL_L2_SRC_SIZE,
DISP_REG_OVL_L2_OFFSET , DISP_REG_OVL_L2_ADDR ,DISP_REG_OVL_L2_PITCH,
DISP_REG_OVL_L2_SRCKEY ,
//layer3
DISP_REG_OVL_RDMA3_CTRL , DISP_REG_OVL_L3_CON ,DISP_REG_OVL_L3_SRC_SIZE,
DISP_REG_OVL_L3_OFFSET , DISP_REG_OVL_L3_ADDR ,DISP_REG_OVL_L3_PITCH,
DISP_REG_OVL_L3_SRCKEY ,
};
reg_back_cnt[idx] = sizeof(regs)/sizeof(unsigned int);
ASSERT(reg_back_cnt[idx] <= OVL_REG_BACK_MAX);
for(i =0; i< reg_back_cnt[idx]; i++)
{
reg_back[idx][i].address = regs[i];
reg_back[idx][i].value = DISP_REG_GET(regs[i]);
}
DDPDBG("store % cnt registers on ovl %d",reg_back_cnt[idx],idx);
}
int ovl_clock_off(DISP_MODULE_ENUM module, void *handle)
{
int idx = ovl_index(module);
DDPMSG("ovl%d_clock_off\n", idx);
#ifdef ENABLE_CLK_MGR
if(ovl_clock_cnt[idx]==0)
{
DDPERR("ovl_deinit, clock off OVL%d, but it's already off! \n", idx);
return 0;
}
if(idx == 0)
{
disable_clock(MT_CG_DISP0_DISP_OVL0, "OVL0");
}
ovl_clock_cnt[idx]--;
#endif
return 0;
}
int OVLROI(DISP_MODULE_ENUM module,
unsigned int bgW,
unsigned int bgH,
unsigned int bgColor,
void * handle)
{
int idx = ovl_index(module);
if((bgW > OVL_MAX_WIDTH) || (bgH > OVL_MAX_HEIGHT))
{
DDPERR("OVLROI(), exceed OVL max size, w=%d, h=%d \n", bgW, bgH);
ASSERT(0);
}
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_ROI_SIZE, bgH<<16 | bgW);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_ROI_BGCLR, bgColor);
return 0;
}
int ovl_reset(DISP_MODULE_ENUM module, void *handle)
{
#define OVL_IDLE (0x3)
int ret = 0;
unsigned int delay_cnt = 0;
int idx = ovl_index(module);
int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
DISP_CPU_REG_SET(idx_offset+DISP_REG_OVL_RST, 0x1);
DISP_CPU_REG_SET(idx_offset+DISP_REG_OVL_RST, 0x0);
/*only wait if not cmdq*/
if (handle == NULL) {
while (!(DISP_REG_GET(idx_offset+DISP_REG_OVL_FLOW_CTRL_DBG) & OVL_IDLE)) {
delay_cnt++;
udelay(10);
if (delay_cnt > 2000) {
DDPERR("ovl%d_reset timeout!\n", idx);
ret = -1;
break;
}
}
}
return ret;
}
void OVLDump(DISP_MODULE_ENUM module)
{
int idx = ovl_index(module);
DDPMSG("== DISP OVL%d ==\n", idx);
DDPMSG("(0x000)O_STA =0x%x\n", DISP_REG_GET(DISP_REG_OVL_STA+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x004)O_INTEN =0x%x\n", DISP_REG_GET(DISP_REG_OVL_INTEN+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x008)O_INTSTA =0x%x\n", DISP_REG_GET(DISP_REG_OVL_INTSTA+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x00c)O_EN =0x%x\n", DISP_REG_GET(DISP_REG_OVL_EN+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x010)O_TRIG =0x%x\n", DISP_REG_GET(DISP_REG_OVL_TRIG+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x014)O_RST =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RST+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x020)O_ROI_SIZE =0x%x\n", DISP_REG_GET(DISP_REG_OVL_ROI_SIZE+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x024)O_PATH_CON =0x%x\n", DISP_REG_GET(DISP_REG_OVL_DATAPATH_CON+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x028)O_ROI_BGCLR =0x%x\n", DISP_REG_GET(DISP_REG_OVL_ROI_BGCLR+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x02c)O_SRC_CON =0x%x\n", DISP_REG_GET(DISP_REG_OVL_SRC_CON+DISP_INDEX_OFFSET*idx));
if(DISP_REG_GET(DISP_REG_OVL_SRC_CON+DISP_INDEX_OFFSET*idx)&0x1)
{
DDPMSG("(0x030)O0_CON =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L0_CON+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x034)O0_SRCKEY =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L0_SRCKEY+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x038)O0_SRC_SIZE =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L0_SRC_SIZE+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x03c)O0_OFFSET =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L0_OFFSET+DISP_INDEX_OFFSET*idx));
DDPMSG("(0xf40)O0_ADDR =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L0_ADDR+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x044)O0_PITCH =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L0_PITCH+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x048)O0_TILE =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L0_TILE+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x0c0)O0_R_CTRL =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA0_CTRL+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x0c8)O0_R_M_GMC_SET1 =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x0cc)O0_R_M_SLOW_CON =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_SLOW_CON+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x0d0)O0_R_FIFO_CTRL =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA0_FIFO_CTRL+DISP_INDEX_OFFSET*idx));
//DDPMSG("(0x1e0)O0_R_M_GMC_SET2 =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING2+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x24c)O0_R_DBG =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA0_DBG+DISP_INDEX_OFFSET*idx));
}
if(DISP_REG_GET(DISP_REG_OVL_SRC_CON+DISP_INDEX_OFFSET*idx)&0x2)
{
DDPMSG("(0x050)O1_CON =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L1_CON+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x054)O1_SRCKEY =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L1_SRCKEY+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x058)O1_SRC_SIZE =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L1_SRC_SIZE+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x05c)O1_OFFSET =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L1_OFFSET+DISP_INDEX_OFFSET*idx));
DDPMSG("(0xf60)O1_ADDR =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L1_ADDR+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x064)O1_PITCH =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L1_PITCH+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x068)O1_TILE =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L1_TILE+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x0e0)O1_R_CTRL =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA1_CTRL+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x0e8)O1_R_M_GMC_SET1 =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x0ec)O1_R_M_SLOW_CON =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_SLOW_CON+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x0f0)O1_R_FIFO_CTRL =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA1_FIFO_CTRL+DISP_INDEX_OFFSET*idx));
//DDPMSG("(0x1e4)O1_R_M_GMC_SET2 =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING2+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x250)O1_R_DBG =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA1_DBG+DISP_INDEX_OFFSET*idx));
}
if(DISP_REG_GET(DISP_REG_OVL_SRC_CON+DISP_INDEX_OFFSET*idx)&0x4)
{
DDPMSG("(0x070)O2_CON =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L2_CON+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x074)O2_SRCKEY =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L2_SRCKEY+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x078)O2_SRC_SIZE =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L2_SRC_SIZE+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x07c)O2_OFFSET =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L2_OFFSET+DISP_INDEX_OFFSET*idx));
DDPMSG("(0xf80)O2_ADDR =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L2_ADDR+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x084)O2_PITCH =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L2_PITCH+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x088)O2_TILE =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L2_TILE+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x100)O2_R_CTRL =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA2_CTRL+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x108)O2_R_M_GMC_SET1 =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x10c)O2_R_M_SLOW_CON =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_SLOW_CON+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x110)O2_R_FIFO_CTRL =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA2_FIFO_CTRL+DISP_INDEX_OFFSET*idx));
//DDPMSG("(0x1e8)O2_R_M_GMC_SET2 =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING2+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x254)O2_R_DBG =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA2_DBG+DISP_INDEX_OFFSET*idx));
}
if(DISP_REG_GET(DISP_REG_OVL_SRC_CON+DISP_INDEX_OFFSET*idx)&0x8)
{
DDPMSG("(0x090)O3_CON =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L3_CON+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x094)O3_SRCKEY =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L3_SRCKEY+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x098)O3_SRC_SIZE =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L3_SRC_SIZE+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x09c)O3_OFFSET =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L3_OFFSET+DISP_INDEX_OFFSET*idx));
DDPMSG("(0xfa0)O3_ADDR =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L3_ADDR+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x0a4)O3_PITCH =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L3_PITCH+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x0a8)O3_TILE =0x%x\n", DISP_REG_GET(DISP_REG_OVL_L3_TILE+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x120)O3_R_CTRL =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA3_CTRL+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x128)O3_R_M_GMC_SET1 =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x12c)O3_R_M_SLOW_CON =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_SLOW_CON+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x130)O3_R_FIFO_CTRL =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA3_FIFO_CTRL+DISP_INDEX_OFFSET*idx));
//DDPMSG("(0x1ec)O3_R_M_GMC_SET2 =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING2+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x258)O3_R_DBG =0x%x\n", DISP_REG_GET(DISP_REG_OVL_RDMA3_DBG+DISP_INDEX_OFFSET*idx));
}
DDPMSG("(0x1d4)O_DBG_MON_SEL =0x%x\n", DISP_REG_GET(DISP_REG_OVL_DEBUG_MON_SEL+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x200)O_DUMMY_REG =0x%x\n", DISP_REG_GET(DISP_REG_OVL_DUMMY_REG+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x240)O_FLOW_CTRL =0x%x\n", DISP_REG_GET(DISP_REG_OVL_FLOW_CTRL_DBG+DISP_INDEX_OFFSET*idx));
DDPMSG("(0x244)O_ADDCON =0x%x\n", DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG+DISP_INDEX_OFFSET*idx));
}
static int ovl_layer_config(DISP_MODULE_ENUM module,
unsigned int layer,
unsigned int source,
DpColorFormat format,
unsigned long addr,
unsigned int src_x, /* ROI x offset*/
unsigned int src_y, /* ROI y offset*/
unsigned int src_pitch,
unsigned int dst_x, /* ROI x offset*/
unsigned int dst_y, /* ROI y offset*/
unsigned int dst_w, /* ROT width*/
unsigned int dst_h, /* ROI height*/
unsigned int key_en,
unsigned int key, /*color key*/
unsigned int aen, /* alpha enable*/
unsigned char alpha,
unsigned int sur_aen,
unsigned int src_alpha,
unsigned int dst_alpha,
unsigned int constant_color,
unsigned int yuv_range,
DISP_BUFFER_TYPE sec,
unsigned int is_engine_sec,
void *handle)
{
int idx = ovl_index(module);
unsigned int value = 0;
enum OVL_INPUT_FORMAT fmt = ovl_input_fmt_convert(format);
unsigned int bpp = ovl_input_fmt_bpp(fmt);
unsigned int input_swap = ovl_input_fmt_byte_swap(fmt);
unsigned int input_fmt = ovl_input_fmt_reg_value(fmt);
enum OVL_COLOR_SPACE space = ovl_input_fmt_color_space(fmt);
unsigned int offset = 0;
/*0100 MTX_JPEG_TO_RGB (YUV FUll TO RGB)*/
int color_matrix = 0x4;
unsigned int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
unsigned int layer_offset = idx_offset + layer * OVL_LAYER_OFFSET;
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
unsigned int bg_h, bg_w;
#endif
switch(yuv_range)
{
case 0: color_matrix = 4; break; //BT601_full
case 1: color_matrix = 6; break; //BT601
case 2: color_matrix = 7; break; //BT709
default:
DDPERR("un-recognized yuv_range=%d! \n", yuv_range);
color_matrix = 4;
}
// DDPMSG("color matrix=%d. \n", color_matrix);
ASSERT((dst_w <= OVL_MAX_WIDTH) &&
(dst_h <= OVL_MAX_HEIGHT) &&
(layer <= 3));
if (addr == 0) {
DDPERR("source from memory, but addr is 0!\n");
ASSERT(0);
}
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
DDPMSG("ovl%d, layer=%d, source=%s, off(x=%d, y=%d), dst(%d, %d, %d, %d),pitch=%d,"
"fmt=%s, addr=%lx, keyEn=%d, key=%d, aen=%d, alpha=%d,"
"sur_aen=%d,sur_alpha=0x%x, constant_color=0x%x, yuv_range=%d, sec=%d,ovlsec=%d\n",
idx, layer, (source==0)?"memory":"dim", src_x, src_y,dst_x, dst_y,
dst_w, dst_h, src_pitch, ovl_intput_format_name(fmt, input_swap),
addr, key_en, key, aen, alpha, sur_aen,
dst_alpha<<2 | src_alpha, constant_color, yuv_range, sec, is_engine_sec);
#endif
if(source==OVL_LAYER_SOURCE_RESERVED) //==1, means constant color
{
if(aen==0)
{
DDPERR("dim layer ahpha enable should be 1!\n");
}
if(fmt!=OVL_INPUT_FORMAT_RGB565 && fmt!=OVL_INPUT_FORMAT_RGB888)
{
//DDPERR("dim layer format should be RGB565");
fmt = OVL_INPUT_FORMAT_RGB888;
input_fmt = ovl_input_fmt_reg_value(fmt);
}
}
// DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_RDMA0_CTRL+layer_offset, 0x1);
value = (REG_FLD_VAL((L_CON_FLD_LARC), (source)) |
REG_FLD_VAL((L_CON_FLD_CFMT), (input_fmt)) |
REG_FLD_VAL((L_CON_FLD_AEN), (aen)) |
REG_FLD_VAL((L_CON_FLD_APHA), (alpha)) |
REG_FLD_VAL((L_CON_FLD_SKEN), (key_en)) |
REG_FLD_VAL((L_CON_FLD_BTSW), (input_swap)));
if (space == OVL_COLOR_SPACE_YUV)
value = value | REG_FLD_VAL((L_CON_FLD_MTX), (color_matrix));
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
value |= 0x600;
#endif
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_CON+layer_offset, value);
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_CLR+idx_offset+layer*4, constant_color);
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_SRC_SIZE+layer_offset,
dst_h<<16 | dst_w);
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
bg_h = DISP_REG_GET(idx_offset + DISP_REG_OVL_ROI_SIZE);
bg_w = bg_h & 0xFFFF;
bg_h = bg_h >> 16;
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_OFFSET+layer_offset, ((bg_h-dst_h-dst_y)<<16)|(bg_w-dst_w-dst_x));
#else
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_OFFSET+layer_offset,
dst_y<<16 | dst_x);
#endif
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
offset = src_pitch*(dst_h+src_y-1)+(src_x+dst_w)*bpp-1;
#else
offset = src_x*bpp+src_y*src_pitch;
#endif
if(!is_engine_sec) {
DISP_REG_SET(handle, DISP_REG_OVL_L0_ADDR+layer_offset, addr+offset);
} else {
unsigned int size;
int m4u_port;
size = (dst_h-1)*src_pitch + dst_w*bpp;
#if defined(MTK_FB_OVL1_SUPPORT)
m4u_port = idx==0 ? M4U_PORT_DISP_OVL0 : M4U_PORT_DISP_OVL1;
#else
m4u_port = M4U_PORT_DISP_OVL0;
#endif
if(sec != DISP_SECURE_BUFFER) {
/* ovl is sec but this layer is non-sec */
/* we need to tell cmdq to help map non-sec mva to sec mva */
cmdqRecWriteSecure(handle, disp_addr_convert(DISP_REG_OVL_L0_ADDR+layer_offset),
CMDQ_SAM_NMVA_2_MVA, addr+offset, 0, size, m4u_port);
} else {
/* for sec layer, addr variable stores sec handle*/
/* we need to pass this handle and offset to cmdq driver */
/* cmdq sec driver will help to convert handle to correct address */
offset = src_x*bpp+src_y*src_pitch;
cmdqRecWriteSecure(handle, disp_addr_convert(DISP_REG_OVL_L0_ADDR+layer_offset),
CMDQ_SAM_H_2_MVA, addr, offset, size, m4u_port);
}
}
if(key_en==1)
{
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_SRCKEY+layer_offset, key);
}
value = (((sur_aen & 0x1) << 15) |
((dst_alpha & 0x3) << 6) | ((dst_alpha & 0x3) << 4) |
((src_alpha & 0x3)<<2) | (src_alpha & 0x3));
value = (REG_FLD_VAL((L_PITCH_FLD_SUR_ALFA), (value)) |
REG_FLD_VAL((L_PITCH_FLD_LSP), (src_pitch)));
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_PITCH+layer_offset, value);
if(idx==0)
{
if(primary_display_is_decouple_mode()==0)
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x6070)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x6070);
}
else
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x50FF)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x50FF);
}
}
if(idx==1)
{
if(primary_display_is_decouple_mode()==0 && ovl_get_status()!=DDP_OVL1_STATUS_SUB)
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x6070)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x6070);
}
else
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x50FF)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x50FF);
}
}
return 0;
}
int OVLLayerConfig(DISP_MODULE_ENUM module,
unsigned int layer,
unsigned int source,
DpColorFormat format,
unsigned int addr,
unsigned int src_x, // ROI x offset
unsigned int src_y, // ROI y offset
unsigned int src_pitch,
unsigned int dst_x, // ROI x offset
unsigned int dst_y, // ROI y offset
unsigned int dst_w, // ROT width
unsigned int dst_h, // ROI height
unsigned int keyEn,
unsigned int key, // color key
unsigned int aen, // alpha enable
unsigned char alpha,
void * handle) {
int idx = ovl_index(module);
unsigned int value = 0;
enum OVL_INPUT_FORMAT fmt = ovl_input_fmt_convert(format);
unsigned int bpp = ovl_input_fmt_bpp(fmt);
unsigned int input_swap = ovl_input_fmt_byte_swap(fmt);
unsigned int input_fmt = ovl_input_fmt_reg_value(fmt);
enum OVL_COLOR_SPACE space = ovl_input_fmt_color_space(fmt);
/*0100 MTX_JPEG_TO_RGB (YUV FUll TO RGB)*/
int color_matrix = 0x4;
unsigned int idx_offset = idx*DISP_INDEX_OFFSET;
unsigned int layer_offset = idx_offset + layer * 0x20;
ASSERT((dst_w <= OVL_MAX_WIDTH) &&
(dst_h <= OVL_MAX_HEIGHT) &&
(layer <= 3));
if (addr == 0) {
DDPERR("source from memory, but addr is 0!\n");
ASSERT(0);
}
DDPDBG("ovl%d, layer=%d, source=%s, off(x=%d, y=%d), dst(%d, %d, %d, %d),pitch=%d,"
"fmt=%s, addr=%lx, keyEn=%d, key=%d, aen=%d, alpha=%d \n",
idx,
layer,
(source==0)?"memory":"constant_color",
src_x,
src_y,
dst_x,
dst_y,
dst_w,
dst_h,
src_pitch,
ovl_intput_format_name(fmt, input_swap),
addr,
keyEn,
key,
aen,
alpha);
if(source==OVL_LAYER_SOURCE_RESERVED) //==1, means constant color
{
if(aen==0)
{
DDPERR("dim layer ahpha enable should be 1!\n");
}
if(fmt!=OVL_INPUT_FORMAT_RGB565)
{
DDPERR("dim layer format should be RGB565");
fmt = OVL_INPUT_FORMAT_RGB565;
}
}
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_CTRL+layer_offset, 0x1);
value = (REG_FLD_VAL((L_CON_FLD_LARC), (source)) |
REG_FLD_VAL((L_CON_FLD_CFMT), (input_fmt)) |
REG_FLD_VAL((L_CON_FLD_AEN), (aen)) |
REG_FLD_VAL((L_CON_FLD_APHA), (alpha)) |
REG_FLD_VAL((L_CON_FLD_SKEN), (keyEn)) |
REG_FLD_VAL((L_CON_FLD_BTSW), (input_swap)));
if (space == OVL_COLOR_SPACE_YUV)
value = value | REG_FLD_VAL((L_CON_FLD_MTX), (color_matrix));
DISP_REG_SET(handle, DISP_REG_OVL_L0_CON+layer_offset, value);
DISP_REG_SET(handle, DISP_REG_OVL_L0_SRC_SIZE+layer_offset,
dst_h<<16 | dst_w);
DISP_REG_SET(handle, DISP_REG_OVL_L0_OFFSET+layer_offset,
dst_y<<16 | dst_x);
DISP_REG_SET(handle, DISP_REG_OVL_L0_ADDR+layer_offset,
addr+src_x*bpp+src_y*src_pitch);
DISP_REG_SET(handle, DISP_REG_OVL_L0_SRCKEY+layer_offset,
key);
value = (REG_FLD_VAL((L_PITCH_FLD_SUR_ALFA), (value)) |
REG_FLD_VAL((L_PITCH_FLD_LSP), (src_pitch)));
DISP_REG_SET(handle, DISP_REG_OVL_L0_PITCH+layer_offset, value);
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x6070);
}
