void ovl_get_info(int idx, void *data) { int i = 0; OVL_BASIC_STRUCT *pdata = (OVL_BASIC_STRUCT *) data; unsigned int idx_offset = idx * DISP_OVL_INDEX_OFFSET; unsigned int layer_off = 0; unsigned int src_on = DISP_REG_GET(DISP_REG_OVL_SRC_CON + idx_offset); OVL_BASIC_STRUCT *p = NULL; memset(pdata, 0, sizeof(OVL_BASIC_STRUCT) * OVL_LAYER_NUM); if (ovl_get_status() == DDP_OVL1_STATUS_SUB || ovl_get_status() == DDP_OVL1_STATUS_IDLE) { /* 4+4 mode */ /* idx=0; */ idx_offset = idx * DISP_OVL_INDEX_OFFSET; src_on = DISP_REG_GET(DISP_REG_OVL_SRC_CON + idx_offset); for (i = 0; i < OVL_LAYER_NUM_PER_OVL; i++) { layer_off = (i % 4) * OVL_LAYER_OFFSET + idx_offset; p = &pdata[i]; p->layer = i; p->layer_en = src_on & (0x1 << i); if (p->layer_en) { p->fmt = (unsigned int) ovl_input_fmt(DISP_REG_GET_FIELD (L_CON_FLD_CFMT, layer_off + DISP_REG_OVL_L0_CON), DISP_REG_GET_FIELD(L_CON_FLD_BTSW, layer_off + DISP_REG_OVL_L0_CON)); p->addr = DISP_REG_GET(layer_off + DISP_REG_OVL_L0_ADDR); p->src_w = DISP_REG_GET(layer_off + DISP_REG_OVL_L0_SRC_SIZE) & 0xfff; p->src_h = (DISP_REG_GET(layer_off + DISP_REG_OVL_L0_SRC_SIZE) >> 16) & 0xfff; p->src_pitch = DISP_REG_GET(layer_off + DISP_REG_OVL_L0_PITCH) & 0xffff; p->bpp = ovl_input_fmt_bpp(DISP_REG_GET_FIELD (L_CON_FLD_CFMT, layer_off + DISP_REG_OVL_L0_CON)); } DDPMSG("ovl_get_info:layer%d,en %d,w %d,h %d,bpp %d,addr %lu\n", i, p->layer_en, p->src_w, p->src_h, p->bpp, p->addr); }
int OVLLayerConfig(DISP_MODULE_ENUM module, unsigned int layer, unsigned int source, DpColorFormat format, unsigned int addr, unsigned int src_x, // ROI x offset unsigned int src_y, // ROI y offset unsigned int src_pitch, unsigned int dst_x, // ROI x offset unsigned int dst_y, // ROI y offset unsigned int dst_w, // ROT width unsigned int dst_h, // ROI height unsigned int keyEn, unsigned int key, // color key unsigned int aen, // alpha enable unsigned char alpha, void * handle) { int idx = ovl_index(module); unsigned int value = 0; enum OVL_INPUT_FORMAT fmt = ovl_input_fmt_convert(format); unsigned int bpp = ovl_input_fmt_bpp(fmt); unsigned int input_swap = ovl_input_fmt_byte_swap(fmt); unsigned int input_fmt = ovl_input_fmt_reg_value(fmt); enum OVL_COLOR_SPACE space = ovl_input_fmt_color_space(fmt); /*0100 MTX_JPEG_TO_RGB (YUV FUll TO RGB)*/ int color_matrix = 0x4; unsigned int idx_offset = idx*DISP_INDEX_OFFSET; unsigned int layer_offset = idx_offset + layer * 0x20; ASSERT((dst_w <= OVL_MAX_WIDTH) && (dst_h <= OVL_MAX_HEIGHT) && (layer <= 3)); if (addr == 0) { DDPERR("source from memory, but addr is 0!\n"); ASSERT(0); } DDPDBG("ovl%d, layer=%d, source=%s, off(x=%d, y=%d), dst(%d, %d, %d, %d),pitch=%d," "fmt=%s, addr=%lx, keyEn=%d, key=%d, aen=%d, alpha=%d \n", idx, layer, (source==0)?"memory":"constant_color", src_x, src_y, dst_x, dst_y, dst_w, dst_h, src_pitch, ovl_intput_format_name(fmt, input_swap), addr, keyEn, key, aen, alpha); if(source==OVL_LAYER_SOURCE_RESERVED) //==1, means constant color { if(aen==0) { DDPERR("dim layer ahpha enable should be 1!\n"); } if(fmt!=OVL_INPUT_FORMAT_RGB565) { DDPERR("dim layer format should be RGB565"); fmt = OVL_INPUT_FORMAT_RGB565; } } DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_CTRL+layer_offset, 0x1); value = (REG_FLD_VAL((L_CON_FLD_LARC), (source)) | REG_FLD_VAL((L_CON_FLD_CFMT), (input_fmt)) | REG_FLD_VAL((L_CON_FLD_AEN), (aen)) | REG_FLD_VAL((L_CON_FLD_APHA), (alpha)) | REG_FLD_VAL((L_CON_FLD_SKEN), (keyEn)) | REG_FLD_VAL((L_CON_FLD_BTSW), (input_swap))); if (space == OVL_COLOR_SPACE_YUV) value = value | REG_FLD_VAL((L_CON_FLD_MTX), (color_matrix)); DISP_REG_SET(handle, DISP_REG_OVL_L0_CON+layer_offset, value); DISP_REG_SET(handle, DISP_REG_OVL_L0_SRC_SIZE+layer_offset, dst_h<<16 | dst_w); DISP_REG_SET(handle, DISP_REG_OVL_L0_OFFSET+layer_offset, dst_y<<16 | dst_x); DISP_REG_SET(handle, DISP_REG_OVL_L0_ADDR+layer_offset, addr+src_x*bpp+src_y*src_pitch); DISP_REG_SET(handle, DISP_REG_OVL_L0_SRCKEY+layer_offset, key); value = (REG_FLD_VAL((L_PITCH_FLD_SUR_ALFA), (value)) | REG_FLD_VAL((L_PITCH_FLD_LSP), (src_pitch))); DISP_REG_SET(handle, DISP_REG_OVL_L0_PITCH+layer_offset, value); DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x6070); }
static int ovl_layer_config(DISP_MODULE_ENUM module, unsigned int layer, unsigned int source, DpColorFormat format, unsigned long addr, unsigned int src_x, /* ROI x offset*/ unsigned int src_y, /* ROI y offset*/ unsigned int src_pitch, unsigned int dst_x, /* ROI x offset*/ unsigned int dst_y, /* ROI y offset*/ unsigned int dst_w, /* ROT width*/ unsigned int dst_h, /* ROI height*/ unsigned int key_en, unsigned int key, /*color key*/ unsigned int aen, /* alpha enable*/ unsigned char alpha, unsigned int sur_aen, unsigned int src_alpha, unsigned int dst_alpha, unsigned int constant_color, unsigned int yuv_range, DISP_BUFFER_TYPE sec, unsigned int is_engine_sec, void *handle) { int idx = ovl_index(module); unsigned int value = 0; enum OVL_INPUT_FORMAT fmt = ovl_input_fmt_convert(format); unsigned int bpp = ovl_input_fmt_bpp(fmt); unsigned int input_swap = ovl_input_fmt_byte_swap(fmt); unsigned int input_fmt = ovl_input_fmt_reg_value(fmt); enum OVL_COLOR_SPACE space = ovl_input_fmt_color_space(fmt); unsigned int offset = 0; /*0100 MTX_JPEG_TO_RGB (YUV FUll TO RGB)*/ int color_matrix = 0x4; unsigned int idx_offset = idx*DISP_OVL_INDEX_OFFSET; unsigned int layer_offset = idx_offset + layer * OVL_LAYER_OFFSET; #ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW unsigned int bg_h, bg_w; #endif switch(yuv_range) { case 0: color_matrix = 4; break; //BT601_full case 1: color_matrix = 6; break; //BT601 case 2: color_matrix = 7; break; //BT709 default: DDPERR("un-recognized yuv_range=%d! \n", yuv_range); color_matrix = 4; } // DDPMSG("color matrix=%d. \n", color_matrix); ASSERT((dst_w <= OVL_MAX_WIDTH) && (dst_h <= OVL_MAX_HEIGHT) && (layer <= 3)); if (addr == 0) { DDPERR("source from memory, but addr is 0!\n"); ASSERT(0); } #if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) DDPMSG("ovl%d, layer=%d, source=%s, off(x=%d, y=%d), dst(%d, %d, %d, %d),pitch=%d," "fmt=%s, addr=%lx, keyEn=%d, key=%d, aen=%d, alpha=%d," "sur_aen=%d,sur_alpha=0x%x, constant_color=0x%x, yuv_range=%d, sec=%d,ovlsec=%d\n", idx, layer, (source==0)?"memory":"dim", src_x, src_y,dst_x, dst_y, dst_w, dst_h, src_pitch, ovl_intput_format_name(fmt, input_swap), addr, key_en, key, aen, alpha, sur_aen, dst_alpha<<2 | src_alpha, constant_color, yuv_range, sec, is_engine_sec); #endif if(source==OVL_LAYER_SOURCE_RESERVED) //==1, means constant color { if(aen==0) { DDPERR("dim layer ahpha enable should be 1!\n"); } if(fmt!=OVL_INPUT_FORMAT_RGB565 && fmt!=OVL_INPUT_FORMAT_RGB888) { //DDPERR("dim layer format should be RGB565"); fmt = OVL_INPUT_FORMAT_RGB888; input_fmt = ovl_input_fmt_reg_value(fmt); } } // DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_RDMA0_CTRL+layer_offset, 0x1); value = (REG_FLD_VAL((L_CON_FLD_LARC), (source)) | REG_FLD_VAL((L_CON_FLD_CFMT), (input_fmt)) | REG_FLD_VAL((L_CON_FLD_AEN), (aen)) | REG_FLD_VAL((L_CON_FLD_APHA), (alpha)) | REG_FLD_VAL((L_CON_FLD_SKEN), (key_en)) | REG_FLD_VAL((L_CON_FLD_BTSW), (input_swap))); if (space == OVL_COLOR_SPACE_YUV) value = value | REG_FLD_VAL((L_CON_FLD_MTX), (color_matrix)); #ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW value |= 0x600; #endif DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_CON+layer_offset, value); DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_CLR+idx_offset+layer*4, constant_color); DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_SRC_SIZE+layer_offset, dst_h<<16 | dst_w); #ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW bg_h = DISP_REG_GET(idx_offset + DISP_REG_OVL_ROI_SIZE); bg_w = bg_h & 0xFFFF; bg_h = bg_h >> 16; DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_OFFSET+layer_offset, ((bg_h-dst_h-dst_y)<<16)|(bg_w-dst_w-dst_x)); #else DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_OFFSET+layer_offset, dst_y<<16 | dst_x); #endif #ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW offset = src_pitch*(dst_h+src_y-1)+(src_x+dst_w)*bpp-1; #else offset = src_x*bpp+src_y*src_pitch; #endif if(!is_engine_sec) { DISP_REG_SET(handle, DISP_REG_OVL_L0_ADDR+layer_offset, addr+offset); } else { unsigned int size; int m4u_port; size = (dst_h-1)*src_pitch + dst_w*bpp; #if defined(MTK_FB_OVL1_SUPPORT) m4u_port = idx==0 ? M4U_PORT_DISP_OVL0 : M4U_PORT_DISP_OVL1; #else m4u_port = M4U_PORT_DISP_OVL0; #endif if(sec != DISP_SECURE_BUFFER) { /* ovl is sec but this layer is non-sec */ /* we need to tell cmdq to help map non-sec mva to sec mva */ cmdqRecWriteSecure(handle, disp_addr_convert(DISP_REG_OVL_L0_ADDR+layer_offset), CMDQ_SAM_NMVA_2_MVA, addr+offset, 0, size, m4u_port); } else { /* for sec layer, addr variable stores sec handle*/ /* we need to pass this handle and offset to cmdq driver */ /* cmdq sec driver will help to convert handle to correct address */ offset = src_x*bpp+src_y*src_pitch; cmdqRecWriteSecure(handle, disp_addr_convert(DISP_REG_OVL_L0_ADDR+layer_offset), CMDQ_SAM_H_2_MVA, addr, offset, size, m4u_port); } } if(key_en==1) { DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_SRCKEY+layer_offset, key); } value = (((sur_aen & 0x1) << 15) | ((dst_alpha & 0x3) << 6) | ((dst_alpha & 0x3) << 4) | ((src_alpha & 0x3)<<2) | (src_alpha & 0x3)); value = (REG_FLD_VAL((L_PITCH_FLD_SUR_ALFA), (value)) | REG_FLD_VAL((L_PITCH_FLD_LSP), (src_pitch))); DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_PITCH+layer_offset, value); if(idx==0) { if(primary_display_is_decouple_mode()==0) { if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x6070) DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x6070); } else { if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x50FF) DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x50FF); } } if(idx==1) { if(primary_display_is_decouple_mode()==0 && ovl_get_status()!=DDP_OVL1_STATUS_SUB) { if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x6070) DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x6070); } else { if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x50FF) DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x50FF); } } return 0; }