void
osiop_pcctwo_attach(struct device *parent, struct device *self, void *aux)
{
struct pcctwosoftc *pcctwo = (struct pcctwosoftc *)parent;
struct osiop_softc *sc = (struct osiop_softc *)self;
struct osiop_pcctwo_softc *psc = (struct osiop_pcctwo_softc *)self;
struct confargs *ca = aux;
int tmp;
extern int cpuspeed;
sc->sc_bst = ca->ca_iot;
sc->sc_dmat = ca->ca_dmat;
if (bus_space_map(sc->sc_bst, ca->ca_paddr, OSIOP_NREGS, 0,
&sc->sc_reg) != 0) {
printf(": couldn't map I/O ports\n");
return;
}
switch (brdtyp) {
#ifdef MVME197
case BRD_197:
sc->sc_clock_freq = cpuspeed;
break;
#endif
#ifdef MVME187
case BRD_187:
case BRD_8120:
sc->sc_clock_freq = cpuspeed * 2;
break;
#endif
default:
sc->sc_clock_freq = 50; /* wild guess */
break;
}
sc->sc_dcntl = OSIOP_DCNTL_EA;
sc->sc_ctest7 = OSIOP_CTEST7_TT1; /* no snooping */
sc->sc_dmode = OSIOP_DMODE_BL4; /* burst length = 4 */
sc->sc_flags = 0;
sc->sc_id = 7; /* XXX should read from CNFG block in nvram */
tmp = bootpart;
if (ca->ca_paddr != bootaddr)
bootpart = -1; /* never match */
osiop_attach(sc);
bootpart = tmp;
psc->sc_ih.ih_fn = osiop_pcctwo_intr;
psc->sc_ih.ih_arg = sc;
psc->sc_ih.ih_wantframe = 0;
psc->sc_ih.ih_ipl = ca->ca_ipl;
/* enable device interrupts */
pcctwointr_establish(PCC2V_SCSI, &psc->sc_ih, self->dv_xname);
bus_space_write_1(pcctwo->sc_iot, pcctwo->sc_ioh,
PCCTWO_SCSIICR, PCC2_IRQ_IEN | (ca->ca_ipl & PCC2_IRQ_IPL));
}
/* ARGSUSED */
void
osiop_pcctwo_attach(device_t parent, device_t self, void *aux)
{
struct pcctwo_attach_args *pa;
struct osiop_pcctwo_softc *sc;
int clk, ctest7;
sc = device_private(self);
pa = aux;
/*
* On the '17x the siop's clock is the same as the CPU clock.
* On the other boards, the siop runs at twice the CPU clock.
* Also, the 17x cannot do proper bus-snooping (the 68060 is
* lame in this repspect) so don't enable it on that board.
*/
#ifdef MVME68K
if (machineid == MVME_172 || machineid == MVME_177) {
clk = cpuspeed;
ctest7 = 0;
} else {
clk = cpuspeed * 2;
ctest7 = OSIOP_CTEST7_SC0;
}
#else
#error Set up siop clock speed for mvme187
#endif
sc->sc_osiop.sc_dev = self;
sc->sc_osiop.sc_bst = pa->pa_bust;
sc->sc_osiop.sc_dmat = pa->pa_dmat;
(void) bus_space_map(sc->sc_osiop.sc_bst, pa->pa_offset, OSIOP_NREGS,
0, &sc->sc_osiop.sc_reg);
sc->sc_osiop.sc_clock_freq = clk;
sc->sc_osiop.sc_ctest7 = ctest7 | OSIOP_CTEST7_TT1;
sc->sc_osiop.sc_dcntl = OSIOP_DCNTL_EA;
sc->sc_osiop.sc_id = 7; /* XXX: Could use NVRAM setting */
/* Attach main MI driver */
osiop_attach(&sc->sc_osiop);
/* Register the event counter */
evcnt_attach_dynamic(&sc->sc_evcnt, EVCNT_TYPE_INTR,
pcctwointr_evcnt(pa->pa_ipl), "disk",
device_xname(sc->sc_osiop.sc_dev));
/* Hook the chip's interrupt */
pcctwointr_establish(PCCTWOV_SCSI, osiop_pcctwo_intr, pa->pa_ipl, sc,
&sc->sc_evcnt);
}
void
osiop_mvme68k_attach(struct device *parent, struct device *self, void *aux)
{
struct osiop_softc *sc = (struct osiop_softc *)self;
struct osiop_mvme68k_softc *psc = (struct osiop_mvme68k_softc *)self;
struct confargs *ca = aux;
int tmp;
extern int cpuspeed;
sc->sc_bst = ca->ca_iot;
sc->sc_dmat = ca->ca_dmat;
if (bus_space_map(sc->sc_bst, (bus_addr_t)ca->ca_paddr, OSIOP_NREGS, 0,
&sc->sc_reg) != 0) {
printf(": couldn't map I/O ports\n");
return;
}
switch (cputyp) {
#ifdef MVME172
case CPU_172: /* XXX this is a guess! Same as MVME177? */
#endif
#ifdef MVME177
case CPU_176:
case CPU_177:
#endif
#if defined(MVME172) || defined(MVME177)
/* MVME177 clock documented as fixed 50MHz in VME177A/HX */
sc->sc_clock_freq = 50;
#if 0
/* No select timeouts on MC68060 */
/* XXX 177 works better with them! */
sc->sc_ctest7 = OSIOP_CTEST7_SC0 | OSIOP_CTEST7_TT1 |
OSIOP_CTEST7_STD;
#else
sc->sc_ctest7 = OSIOP_CTEST7_SC0 | OSIOP_CTEST7_TT1;
#endif
break;
#endif
default:
/* XXX does the clock frequency change for 33MHz processors? */
sc->sc_clock_freq = cpuspeed * 2;
sc->sc_ctest7 = OSIOP_CTEST7_SC0 | OSIOP_CTEST7_TT1;
break;
}
sc->sc_dcntl = OSIOP_DCNTL_EA;
sc->sc_dmode = OSIOP_DMODE_BL4; /* burst length = 4 */
sc->sc_flags = 0;
sc->sc_id = 7; /* XXX should read from CNFG block in nvram */
tmp = bootpart;
if (ca->ca_paddr != bootaddr)
bootpart = -1; /* never match */
osiop_attach(sc);
bootpart = tmp;
psc->sc_ih.ih_fn = osiop_mvme68k_intr;
psc->sc_ih.ih_arg = sc;
psc->sc_ih.ih_wantframe = 0;
psc->sc_ih.ih_ipl = ca->ca_ipl;
/* enable device interrupts */
switch (ca->ca_bustype) {
#if NMC > 0
case BUS_MC:
mcintr_establish(MCV_NCR, &psc->sc_ih, self->dv_xname);
sys_mc->mc_ncrirq = ca->ca_ipl | MC_IRQ_IEN;
break;
#endif
#if NPCCTWO > 0
case BUS_PCCTWO:
pcctwointr_establish(PCC2V_NCR, &psc->sc_ih, self->dv_xname);
sys_pcc2->pcc2_ncrirq = ca->ca_ipl | PCC2_IRQ_IEN;
break;
#endif
}
}
/* ARGSUSED */
void
ie_pcctwo_attach(device_t parent, device_t self, void *aux)
{
struct pcctwo_attach_args *pa;
struct ie_pcctwo_softc *ps;
struct ie_softc *sc;
bus_dma_segment_t seg;
int rseg;
pa = aux;
ps = device_private(self);
sc = &ps->ps_ie;
sc->sc_dev = self;
/* Map the MPU controller registers in PCCTWO space */
ps->ps_bust = pa->pa_bust;
bus_space_map(pa->pa_bust, pa->pa_offset, IE_MPUREG_SIZE,
0, &ps->ps_bush);
/* Get contiguous DMA-able memory for the IE chip */
if (bus_dmamem_alloc(pa->pa_dmat, ether_data_buff_size, PAGE_SIZE, 0,
&seg, 1, &rseg,
BUS_DMA_NOWAIT | BUS_DMA_ONBOARD_RAM | BUS_DMA_24BIT) != 0) {
aprint_error_dev(self, "Failed to allocate ether buffer\n");
return;
}
if (bus_dmamem_map(pa->pa_dmat, &seg, rseg, ether_data_buff_size,
(void **) & sc->sc_maddr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) {
aprint_error_dev(self, "Failed to map ether buffer\n");
bus_dmamem_free(pa->pa_dmat, &seg, rseg);
return;
}
sc->bt = pa->pa_bust;
sc->bh = (bus_space_handle_t) sc->sc_maddr; /* XXXSCW Better way? */
sc->sc_iobase = (void *) seg.ds_addr;
sc->sc_msize = ether_data_buff_size;
memset(sc->sc_maddr, 0, ether_data_buff_size);
sc->hwreset = ie_reset;
sc->hwinit = ie_hwinit;
sc->chan_attn = ie_atten;
sc->intrhook = ie_intrhook;
sc->memcopyin = ie_copyin;
sc->memcopyout = ie_copyout;
sc->ie_bus_barrier = NULL;
sc->ie_bus_read16 = ie_read_16;
sc->ie_bus_write16 = ie_write_16;
sc->ie_bus_write24 = ie_write_24;
sc->sc_mediachange = NULL;
sc->sc_mediastatus = NULL;
sc->scp = 0;
sc->iscp = sc->scp + ((IE_SCP_SZ + 15) & ~15);
sc->scb = sc->iscp + IE_ISCP_SZ;
sc->buf_area = sc->scb + IE_SCB_SZ;
sc->buf_area_sz = sc->sc_msize - (sc->buf_area - sc->scp);
/*
* BUS_USE -> Interrupt Active High (edge-triggered),
* Lock function enabled,
* Internal bus throttle timer triggering,
* 82586 operating mode.
*/
ie_write_16(sc, IE_SCP_BUS_USE(sc->scp), IE_BUS_USE);
ie_write_24(sc, IE_SCP_ISCP(sc->scp), sc->iscp);
ie_write_16(sc, IE_ISCP_SCB(sc->iscp), sc->scb);
ie_write_24(sc, IE_ISCP_BASE(sc->iscp), sc->scp);
/* This has the side-effect of resetting the chip */
i82586_proberam(sc);
/* Attach the MI back-end */
i82586_attach(sc, "onboard", mvme_ea, NULL, 0, 0);
/* Register the event counter */
evcnt_attach_dynamic(&ps->ps_evcnt, EVCNT_TYPE_INTR,
pcctwointr_evcnt(pa->pa_ipl), "ether", device_xname(self));
/* Finally, hook the hardware interrupt */
pcctwointr_establish(PCCTWOV_LANC_IRQ, i82586_intr, pa->pa_ipl, sc,
&ps->ps_evcnt);
}
