void early_pch_init(void) { pch_enable_lpc(); pch_enable_bars(); pch_generic_setup(); setup_pch_gpios(&mainboard_gpio_map); }
void pch_early_init(void) { reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script); pch_enable_lpc(); enable_smbus(); /* 8.14 Additional PCI Express Programming Steps, step #1 */ pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0); pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80); pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30); }
void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBABASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00,0xa4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, .max_ddr3_freq = 1333, .usb_port_config = { { 1, 0, 0x0080 }, /* P0: Front port (OC0) */ { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ { 1, 2, 0x0080 }, /* P4: Front port (OC2) */ { 0, 0, 0x0000 }, /* P5: Empty */ { 0, 0, 0x0000 }, /* P6: Empty */ { 0, 0, 0x0000 }, /* P7: Empty */ { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ { 0, 4, 0x0000 }, /* P11: Empty */ { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ }, }; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (bist == 0) enable_lapic(); pch_enable_lpc(); /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&stumpy_gpio_map); setup_sio_gpios(); /* Early SuperIO setup */ it8772f_ac_resume_southbridge(DUMMY_DEV); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); init_bootmode_straps(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected\n"); boot_mode = 1; /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); /* Prepare USB controller early in S3 resume */ if (boot_mode == 2) { /* * For Stumpy the back USB ports are reset on resume * so default to resetting the controller to make the * kernel happy. There is a CMOS flag to disable the * controller reset in case the kernel can tolerate * the device power loss better in the future. */ u8 magic = cmos_read(CMOS_USB_RESET_DISABLE); if (magic == USB_RESET_DISABLE_MAGIC) { printk(BIOS_DEBUG, "USB Controller Reset Disabled\n"); enable_usb_bar(); } else { printk(BIOS_DEBUG, "USB Controller Reset Enabled\n"); } } else { /* Ensure USB reset on resume is enabled at boot */ cmos_write(0, CMOS_USB_RESET_DISABLE); } post_code(0x39); pei_data.boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3a); /* Perform some initialization that must run before stage2 */ early_pch_init(); post_code(0x3b); rcba_config(); post_code(0x3c); quick_ram_check(); post_code(0x3e); cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); if (CONFIG_LPC_TPM) { init_tpm(boot_mode == 2); } }
void main(unsigned long bist) { int s3resume = 0; spd_raw_data spd[4]; if (MCHBAR16(SSKPD) == 0xCAFE) { outb(0x6, 0xcf9); halt (); } timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (bist == 0) enable_lapic(); pch_enable_lpc(); /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&mainboard_gpio_map); early_usb_init(mainboard_usb_ports); /* Initialize console device(s) */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); /* Perform some early chipset initialization required * before RAM initialization can work */ sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); s3resume = southbridge_detect_s3_resume(); post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); post_code(0x39); post_code(0x3a); memset (spd, 0, sizeof (spd)); mainboard_get_spd(spd); timestamp_add_now(TS_BEFORE_INITRAM); init_dram_ddr3(spd, 1, get_mem_min_tck(), s3resume); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c); southbridge_configure_default_intmap(); rcba_config(); post_code(0x3d); northbridge_romstage_finalize(s3resume); #if CONFIG_LPC_TPM init_tpm(s3resume); #endif post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); }
void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBABASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ { 1, 2, 0x0040 }, /* P4: Front port (OC2) */ { 0, 0, 0x0000 }, /* P5: Empty */ { 0, 0, 0x0000 }, /* P6: Empty */ { 0, 0, 0x0000 }, /* P7: Empty */ { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ { 0, 4, 0x0000 }, /* P11: Empty */ { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ }, }; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (bist == 0) enable_lapic(); pch_enable_lpc(); /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&emeraldlake2_gpio_map); setup_sio_gpios(); /* Early SuperIO setup */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected\n"); boot_mode = 1; /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); /* Prepare USB controller early in S3 resume */ if (boot_mode == 2) enable_usb_bar(); post_code(0x3a); pei_data.boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3b); /* Perform some initialization that must run before stage2 */ early_pch_init(); post_code(0x3c); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); post_code(0x3d); quick_ram_check(); post_code(0x3e); cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); if (CONFIG_LPC_TPM) { init_tpm(boot_mode == 2); } }
void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBABASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ { 0, 3, 0x0000 }, /* P0: Empty */ { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ { 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */ { 0, 3, 0x0000 }, /* P4: Empty */ { 0, 3, 0x0000 }, /* P5: Empty */ { 0, 3, 0x0000 }, /* P6: Empty */ { 0, 3, 0x0000 }, /* P7: Empty */ /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ { 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */ { 0, 4, 0x0000 }, /* P9: Empty */ { 1, 4, 0x0040 }, /* P10: Camera (no OC) */ { 0, 4, 0x0000 }, /* P11: Empty */ { 0, 4, 0x0000 }, /* P12: Empty */ { 0, 4, 0x0000 }, /* P13: Empty */ }, }; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (bist == 0) enable_lapic(); pch_enable_lpc(); /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&parrot_gpio_map); /* Initialize console device(s) */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected\n"); boot_mode = 1; /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); /* Prepare USB controller early in S3 resume */ if (boot_mode == 2) enable_usb_bar(); post_code(0x39); post_code(0x3a); pei_data.boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c); rcba_config(); post_code(0x3d); quick_ram_check(); post_code(0x3e); cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); #endif timestamp_add_now(TS_END_ROMSTAGE); }
void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = DEFAULT_PCIEXBAR, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, .system_type = 5, /* ULT */ .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ec_present = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, // Enable 2x refresh mode .ddr_refresh_2x = 1, .dq_pins_interleaved = 1, .max_ddr3_freq = 1600, .usb_xhci_on_resume = 1, .usb2_ports = { /* Length, Enable, OCn#, Location */ { 0x0064, 1, 0, /* P0: VP8 */ USB_PORT_MINI_PCIE }, { 0x0040, 1, 0, /* P1: Port A, CN22 */ USB_PORT_INTERNAL }, { 0x0040, 1, 1, /* P2: Port B, CN23 */ USB_PORT_INTERNAL }, { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */ USB_PORT_INTERNAL }, { 0x0040, 1, 2, /* P4: Port C, CN25 */ USB_PORT_INTERNAL }, { 0x0040, 1, 2, /* P5: Port D, CN25 */ USB_PORT_INTERNAL }, { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */ USB_PORT_INTERNAL }, { 0x0000, 0, 0, /* P7: N/C */ USB_PORT_SKIP }, }, .usb3_ports = { /* Enable, OCn# */ { 1, 0 }, /* P1; CN22 */ { 1, 1 }, /* P2; CN23 */ { 1, 2 }, /* P3; CN25 */ { 1, 2 }, /* P4; CN25 */ }, }; struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .bist = bist, }; /* Early SuperIO setup */ ite_kill_watchdog(IT8772F_GPIO_DEV); it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV); pch_enable_lpc(); ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); /* Turn on Power LED GP22 for Tricky */ it8772f_gpio_led(IT8772F_GPIO_DEV, 2 /* set */, 0xF7 /* select */, 0x04 /* polarity: inverting */, 0x00 /* 0=pulldown */, 0x04 /* output */, 0x04 /* 1=Simple IO function */, SIO_GPIO_BLINK_GPIO22, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); }