static void usb_xhci_clock_gating(struct device *dev) { u32 reg32; u16 reg16; /* IOBP 0xE5004001[7:6] = 11b */ pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); reg32 = pci_read_config32(dev, 0x40); reg32 &= ~(1 << 23); /* unsupported request */ if (pch_is_lp()) { /* D20:F0:40h[18,17,8] = 111b */ reg32 |= (1 << 18) | (1 << 17) | (1 << 8); /* D20:F0:40h[21,20,19] = 110b to enable XHCI Idle L1 */ reg32 &= ~(1 << 19); reg32 |= (1 << 21) | (1 << 20); } else { /* D20:F0:40h[21,20,18,17,8] = 11111b */ reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8); } /* Avoid writing upper byte as it is write-once */ pci_write_config16(dev, 0x40, (u16)(reg32 & 0xffff)); pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff)); /* D20:F0:44h[9,7,3] = 111b */ reg16 = pci_read_config16(dev, 0x44); reg16 |= (1 << 9) | (1 << 7) | (1 << 3); pci_write_config16(dev, 0x44, reg16); reg32 = pci_read_config32(dev, 0xa0); if (pch_is_lp()) { /* D20:F0:A0h[18] = 1 */ reg32 |= (1 << 18); } else { /* D20:F0:A0h[6] = 1 */ reg32 |= (1 << 6); } pci_write_config32(dev, 0xa0, reg32); /* D20:F0:A4h[13] = 0 */ reg32 = pci_read_config32(dev, 0xa4); reg32 &= ~(1 << 13); pci_write_config32(dev, 0xa4, reg32); }
static int usb_xhci_port_count_usb3(struct device *dev) #endif { if (pch_is_lp()) { /* LynxPoint-LP has 4 SS ports */ return 4; } /* LynxPoint-H can have 0, 2, 4, or 6 SS ports */ u8 *mem_base = usb_xhci_mem_base(dev); u32 fus = read32(mem_base + XHCI_USB3FUS); fus >>= XHCI_USB3FUS_SS_SHIFT; fus &= XHCI_USB3FUS_SS_MASK; switch (fus) { case 3: return 0; case 2: return 2; case 1: return 4; case 0: default: return 6; } }
/* Handler for XHCI controller on entry to S3/S4/S5 */ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) { u16 reg16; u32 reg32; u8 *mem_base = usb_xhci_mem_base(dev); if (!mem_base || slp_typ < ACPI_S3) return; if (pch_is_lp()) { /* Set D0 state */ reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); reg16 &= ~PWR_CTL_SET_MASK; reg16 |= PWR_CTL_SET_D0; pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); /* Clear PCI 0xB0[14:13] */ reg32 = pci_read_config32(dev, 0xb0); reg32 &= ~((1 << 14) | (1 << 13)); pci_write_config32(dev, 0xb0, reg32); /* Clear MMIO 0x816c[14,2] */ reg32 = read32(mem_base + 0x816c); reg32 &= ~((1 << 14) | (1 << 2)); write32(mem_base + 0x816c, reg32); /* Reset disconnected USB3 ports */ usb_xhci_reset_usb3(dev, 0); /* Set MMIO 0x80e0[15] */ reg32 = read32(mem_base + 0x80e0); reg32 |= (1 << 15); write32(mem_base + 0x80e0, reg32); } /* Set D3Hot state and enable PME */ pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_SET_D3); pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_STATUS_PME); pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME); }
/* Route all ports to XHCI controller */ void usb_xhci_route_all(void) { u32 port_mask, route; u16 reg16; /* Skip if EHCI is already disabled */ if (RCBA32(FD) & PCH_DISABLE_EHCI1) return; /* Set D0 state */ reg16 = pci_read_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS); reg16 &= ~PWR_CTL_SET_MASK; reg16 |= PWR_CTL_SET_D0; pci_write_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS, reg16); /* Set USB3 superspeed enable */ port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PRM); route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PR); route &= ~XHCI_USB3PR_SSEN; route |= XHCI_USB3PR_SSEN & port_mask; pci_write_config32(PCH_XHCI_DEV, XHCI_USB3PR, route); /* Route USB2 ports to XHCI controller */ port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PRM); route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PR); route &= ~XHCI_USB2PR_HCSEL; route |= XHCI_USB2PR_HCSEL & port_mask; pci_write_config32(PCH_XHCI_DEV, XHCI_USB2PR, route); /* Disable EHCI controller */ usb_ehci_disable(PCH_EHCI1_DEV); /* LynxPoint-H has a second EHCI controller */ if (!pch_is_lp()) usb_ehci_disable(PCH_EHCI2_DEV); /* Reset and clear port change status */ usb_xhci_reset_usb3(PCH_XHCI_DEV, 1); }
void enable_usb_bar(void) { enable_usb_bar_on_device(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0); if (!pch_is_lp()) enable_usb_bar_on_device(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0); }
static void sata_init(struct device *dev) { u32 reg32; u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; printk(BIOS_DEBUG, "SATA: Initializing...\n"); if (config == NULL) { printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); return; } /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); if (config->ide_legacy_combined) { printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); /* And without AHCI BAR no memory decoding */ reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); pci_write_config8(dev, 0x09, 0x80); /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); /* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); /* Set IDE I/O Configuration */ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* Port enable */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; reg16 |= config->sata_port_map; pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } else if(config->sata_ahci) { u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0x0a); /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); /* Set IDE I/O Configuration */ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16); udelay(2); /* Setup register 98h */ reg32 = pci_read_config16(dev, 0x98); reg32 |= 1 << 19; /* BWG step 6 */ reg32 |= 1 << 22; /* BWG step 5 */ reg32 &= ~(0x3f << 7); reg32 |= 0x04 << 7; /* BWG step 7 */ reg32 |= 1 << 20; /* BWG step 8 */ reg32 &= ~(0x03 << 5); reg32 |= 1 << 5; /* BWG step 9 */ reg32 |= 1 << 18; /* BWG step 10 */ reg32 |= 1 << 29; /* BWG step 11 */ if (pch_is_lp()) { reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ } pci_write_config32(dev, 0x98, reg32); /* Setup register 9Ch */ reg16 = 0; /* Disable alternate ID */ reg16 = 1 << 5; /* BWG step 12 */ pci_write_config16(dev, 0x9c, reg16); /* SATA Initialization register */ reg32 = 0x183; reg32 |= (config->sata_port_map ^ 0x3f) << 24; reg32 |= (config->sata_devslp_mux & 1) << 15; pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %08X\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS if (pch_is_lp()) reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); (void) read32(abar + 0x0c); /* Read back 1 */ (void) read32(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); /* Enable DEVSLP */ if (pch_is_lp()) { if (config->sata_devslp_disable) reg32 &= ~(1 << 3); else reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); } else { reg32 &= ~0x00000002; } write32(abar + 0x24, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); /* And without AHCI BAR no memory decoding */ reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); /* Native mode capable on both primary and secondary (0xa) * or'ed with enabled (0x50) = 0xf */ pci_write_config8(dev, 0x09, 0x8f); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0xff); /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_SITRE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); /* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); /* Set IDE I/O Configuration */ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* Port enable */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; reg16 |= config->sata_port_map; pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } /* Set Gen3 Transmitter settings if needed */ if (config->sata_port0_gen3_tx) pch_iobp_update(SATA_IOBP_SP0G3IR, 0, config->sata_port0_gen3_tx); if (config->sata_port1_gen3_tx) pch_iobp_update(SATA_IOBP_SP1G3IR, 0, config->sata_port1_gen3_tx); /* Set Gen3 DTLE DATA / EDGE registers if needed */ if (config->sata_port0_gen3_dtle) { pch_iobp_update(SATA_IOBP_SP0DTLE_DATA, ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) << SATA_DTLE_DATA_SHIFT); pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE, ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) << SATA_DTLE_EDGE_SHIFT); } if (config->sata_port1_gen3_dtle) { pch_iobp_update(SATA_IOBP_SP1DTLE_DATA, ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) << SATA_DTLE_DATA_SHIFT); pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE, ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) << SATA_DTLE_EDGE_SHIFT); } /* Additional Programming Requirements */ /* Power Optimizer */ /* Step 1 */ if (pch_is_lp()) sir_write(dev, 0x64, 0x883c9003); else sir_write(dev, 0x64, 0x883c9001); /* Step 2: SIR 68h[15:0] = 880Ah */ reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; reg32 |= 0x880a; sir_write(dev, 0x68, reg32); /* Step 3: SIR 60h[3] = 1 */ reg32 = sir_read(dev, 0x60); reg32 |= (1 << 3); sir_write(dev, 0x60, reg32); /* Step 4: SIR 60h[0] = 1 */ reg32 = sir_read(dev, 0x60); reg32 |= (1 << 0); sir_write(dev, 0x60, reg32); /* Step 5: SIR 60h[1] = 1 */ reg32 = sir_read(dev, 0x60); reg32 |= (1 << 1); sir_write(dev, 0x60, reg32); /* Clock Gating */ sir_write(dev, 0x70, 0x3f00bf1f); if (pch_is_lp()) { sir_write(dev, 0x54, 0xcf000f0f); sir_write(dev, 0x58, 0x00190000); } reg32 = pci_read_config32(dev, 0x300); reg32 |= (1 << 17) | (1 << 16); reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); }
static void azalia_pch_init(struct device *dev, u8 *base) { u8 reg8; u16 reg16; u32 reg32; if (RCBA32(0x2030) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 25); reg32 |= RCBA32(0x2030) & 0xfe; pci_write_config32(dev, 0x120, reg32); if (!pch_is_lp()) { reg16 = pci_read_config16(dev, 0x78); reg16 &= ~(1 << 11); pci_write_config16(dev, 0x78, reg16); } } else printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); reg32 = pci_read_config32(dev, 0x114); reg32 &= ~0xfe; pci_write_config32(dev, 0x114, reg32); // Set VCi enable bit if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) { reg32 = pci_read_config32(dev, 0x120); if (pch_is_lp()) reg32 &= ~(1 << 31); else reg32 |= (1 << 31); pci_write_config32(dev, 0x120, reg32); } reg8 = pci_read_config8(dev, 0x43); if (pch_is_lp()) reg8 &= ~(1 << 6); else reg8 |= (1 << 4); pci_write_config8(dev, 0x43, reg8); if (!pch_is_lp()) { reg32 = pci_read_config32(dev, 0xc0); reg32 |= (1 << 17); pci_write_config32(dev, 0xc0, reg32); } /* Additional programming steps */ reg32 = pci_read_config32(dev, 0xc4); if (pch_is_lp()) reg32 |= (1 << 24); else reg32 |= (1 << 14); pci_write_config32(dev, 0xc4, reg32); if (!pch_is_lp()) { reg32 = pci_read_config32(dev, 0xd0); reg32 &= ~(1 << 31); pci_write_config32(dev, 0xd0, reg32); } reg8 = pci_read_config8(dev, 0x40); // Audio Control reg8 |= 1; // Select Azalia mode pci_write_config8(dev, 0x40, reg8); reg8 = pci_read_config8(dev, 0x4d); // Docking Status reg8 &= ~(1 << 7); // Docking not supported pci_write_config8(dev, 0x4d, reg8); if (pch_is_lp()) { reg16 = read32(base + 0x0012); reg16 |= (1 << 0); write32(base + 0x0012, reg16); /* disable Auto Voltage Detector */ reg8 = pci_read_config8(dev, 0x42); reg8 |= (1 << 2); pci_write_config8(dev, 0x42, reg8); } }
static void usb_xhci_init(device_t dev) { u32 reg32; u16 reg16; u32 mem_base = usb_xhci_mem_base(dev); config_t *config = dev->chip_info; /* D20:F0:74h[1:0] = 00b (set D0 state) */ reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); reg16 &= ~PWR_CTL_SET_MASK; reg16 |= PWR_CTL_SET_D0; pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); /* Enable clock gating first */ usb_xhci_clock_gating(dev); reg32 = read32(mem_base + 0x8144); if (pch_is_lp()) { /* XHCIBAR + 8144h[8,7,6] = 111b */ reg32 |= (1 << 8) | (1 << 7) | (1 << 6); } else { /* XHCIBAR + 8144h[8,7,6] = 100b */ reg32 &= ~((1 << 7) | (1 << 6)); reg32 |= (1 << 8); } write32(mem_base + 0x8144, reg32); if (pch_is_lp()) { /* XHCIBAR + 816Ch[19:0] = 000e0038h */ reg32 = read32(mem_base + 0x816c); reg32 &= ~0x000fffff; reg32 |= 0x000e0038; write32(mem_base + 0x816c, reg32); /* D20:F0:B0h[17,14,13] = 100b */ reg32 = pci_read_config32(dev, 0xb0); reg32 &= ~((1 << 14) | (1 << 13)); reg32 |= (1 << 17); pci_write_config32(dev, 0xb0, reg32); } reg32 = pci_read_config32(dev, 0x50); if (pch_is_lp()) { /* D20:F0:50h[28:0] = 0FCE2E5Fh */ reg32 &= ~0x1fffffff; reg32 |= 0x0fce2e5f; } else { /* D20:F0:50h[26:0] = 07886E9Fh */ reg32 &= ~0x07ffffff; reg32 |= 0x07886e9f; } pci_write_config32(dev, 0x50, reg32); /* D20:F0:44h[31] = 1 (Access Control Bit) */ reg32 = pci_read_config32(dev, 0x44); reg32 |= (1 << 31); pci_write_config32(dev, 0x44, reg32); /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ reg32 = pci_read_config32(dev, 0x40); reg32 &= ~(1 << 23); /* unsupported request */ reg32 |= (1 << 31); pci_write_config32(dev, 0x40, reg32); #if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type == 3) { /* Reset ports that are disabled or * polling before returning to the OS. */ usb_xhci_reset_usb3(dev, 0); } else #endif /* Route all ports to XHCI */ if (config->xhci_default) outb(0xca, 0xb2); }
void pch_log_state(void) { u16 pm1_sts, gen_pmcon_3, tco2_sts; u8 gen_pmcon_2; struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (!lpc) return; pm1_sts = inw(get_pmbase() + PM1_STS); tco2_sts = inw(get_pmbase() + TCO2_STS); gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); /* PWR_FLR Power Failure */ if (gen_pmcon_2 & (1 << 0)) elog_add_event(ELOG_TYPE_POWER_FAIL); /* SUS Well Power Failure */ if (gen_pmcon_3 & (1 << 14)) elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); /* SYS_PWROK Failure */ if (gen_pmcon_2 & (1 << 1)) elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL); /* PWROK Failure */ if (gen_pmcon_2 & (1 << 0)) elog_add_event(ELOG_TYPE_PWROK_FAIL); /* Second TCO Timeout */ if (tco2_sts & (1 << 1)) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ if (pm1_sts & (1 << 11)) elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); /* System Reset Status (reset button pushed) */ if (gen_pmcon_2 & (1 << 4)) elog_add_event(ELOG_TYPE_RESET_BUTTON); /* General Reset Status */ if (gen_pmcon_3 & (1 << 9)) elog_add_event(ELOG_TYPE_SYSTEM_RESET); /* ACPI Wake */ if (pm1_sts & (1 << 15)) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, acpi_is_wakeup_s3() ? 3 : 5); /* * Wake sources */ /* Power Button */ if (pm1_sts & (1 << 8)) elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); /* RTC */ if (pm1_sts & (1 << 10)) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); /* PCI Express (TODO: determine wake device) */ if (pm1_sts & (1 << 14)) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); /* GPE */ if (pch_is_lp()) pch_lp_log_gpe(); else pch_log_gpe(); }
static void usb_xhci_init(device_t dev) { u32 reg32; u16 reg16; u32 mem_base = usb_xhci_mem_base(dev); /* D20:F0:74h[1:0] = 00b (set D0 state) */ reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); reg16 &= ~PWR_CTL_SET_MASK; reg16 |= PWR_CTL_SET_D0; pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); /* Enable clock gating first */ usb_xhci_clock_gating(dev); reg32 = read32(mem_base + 0x8144); if (pch_is_lp()) { /* XHCIBAR + 8144h[8,7,6] = 111b */ reg32 |= (1 << 8) | (1 << 7) | (1 << 6); } else { /* XHCIBAR + 8144h[8,7,6] = 100b */ reg32 &= ~((1 << 7) | (1 << 6)); reg32 |= (1 << 8); } write32(mem_base + 0x8144, reg32); if (pch_is_lp()) { /* XHCIBAR + 816Ch[19:0] = 000e0038h */ reg32 = read32(mem_base + 0x816c); reg32 &= ~0x000fffff; reg32 |= 0x000e0038; write32(mem_base + 0x816c, reg32); /* D20:F0:B0h[17,14,13] = 100b */ reg32 = pci_read_config32(dev, 0xb0); reg32 &= ~((1 << 14) | (1 << 13)); reg32 |= (1 << 17); pci_write_config32(dev, 0xb0, reg32); } reg32 = pci_read_config32(dev, 0x50); if (pch_is_lp()) { /* D20:F0:50h[28:0] = 0FCE2E5Fh */ reg32 &= ~0x1fffffff; reg32 |= 0x0fce2e5f; } else { /* D20:F0:50h[26:0] = 07886E9Fh */ reg32 &= ~0x07ffffff; reg32 |= 0x07886e9f; } pci_write_config32(dev, 0x50, reg32); /* D20:F0:44h[31] = 1 (Access Control Bit) */ reg32 = pci_read_config32(dev, 0x44); reg32 |= (1 << 31); pci_write_config32(dev, 0x44, reg32); /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ reg32 = pci_read_config32(dev, 0x40); reg32 &= ~(1 << 23); /* unsupported request */ reg32 |= (1 << 31); pci_write_config32(dev, 0x40, reg32); /* Enable ports that are disabled before returning to OS */ if (acpi_is_wakeup_s3()) usb_xhci_enable_ports_usb3(dev); }