LOCAL void sysPciAutoconfigPostEnumBridgeInit
(
PCI_SYSTEM *pSys, /* PCI_SYSTEM structure pointer */
PCI_LOC *pLoc, /* pointer to function in question */
UINT devVend /* deviceID/vendorID of device */
)
{
if (devVend == API_DEVICE(API_STURGEON))
{
UINT32 readParams;
UINT32 intMap;
UINT32 t, offset;
/* set up READ register: Prefetch enable, 2 lines of fetch ahead */
readParams = (2 << 5) | (2 << 2) | 0x3;
pciConfigOutLong (pLoc->bus, pLoc->device, pLoc->function,
LPB_CFG_READ, readParams);
/* Setup interrupt mapping for Block 1:
Enabled, Dest=Logical (CPU 0), Type=Fixed, Trigger=Edge */
intMap = (LPB_INT_CTRL_ENABLE |
LPB_INT_CTRL_DESTMODE | /* Logical */
(0x1 << LPB_INT_CTRL_DEST_SHIFT) | /* CPU 0 */
(0x0 << LPB_INT_CTRL_MSGTYPE_SHIFT)); /* Fixed */
/* For the SWARM and CSWARMs, the LDT Host Bridge is assumed to
have the base interrupt mapping (by convention) and the
LDT device number is the effective "slot" number. */
offset = pLoc->device;
t = (intMap + offset);
offset = (offset+1) % 4;
t |= (intMap + offset) << 16;
pciConfigOutLong (pLoc->bus, pLoc->device, pLoc->function,
LPB_CFG_INT_CTRL_BASE + 8, t);
offset = (offset+1) % 4;
t = (intMap + offset);
offset = (offset+1) % 4;
t |= (intMap + offset) << 16;
pciConfigOutLong (pLoc->bus, pLoc->device, pLoc->function,
LPB_CFG_INT_CTRL_BASE + 12, t);
pciConfigInLong (pLoc->bus, pLoc->device, pLoc->function,
LPB_CFG_INT_BLOCK1, &t);
t &= 0xFFFFFF00;
t |= (0x40 | (BCM1250_PCI_LDT_INT_MAP(BCM1250_PCI_INT_BASE) >> 2));
pciConfigOutLong (pLoc->bus, pLoc->device, pLoc->function,
LPB_CFG_INT_BLOCK1, t);
}
void
osl_pci_write_config(osl_t *osh, unsigned int offset, unsigned int size, unsigned int val)
{
uint retry = PCI_CFG_RETRY; /* PR15065: faulty cardbus controller bug */
pciinfo_t *pciinfo = (pciinfo_t *)(osh->devinfo);
ASSERT(size == 4);
do {
pciConfigOutLong(pciinfo->bus, pciinfo->dev, pciinfo->func, offset, val);
/* PR15065: PCI_BAR0_WIN is believed to be the only pci cfg write that can occur
* when dma activity is possible
*/
if (offset != PCI_BAR0_WIN)
break;
if (osl_pci_read_config(osh, offset, size) == val)
break;
} while (retry--);
#ifdef BCMDBG
if (retry < PCI_CFG_RETRY)
printf("PCI CONFIG WRITE access to %d required %d retries\n", offset,
(PCI_CFG_RETRY - retry));
#endif /* BCMDBG */
}
int pci_config_putw(pci_dev_t *dev, uint32 addr, uint32 data)
{
STATUS requestStatus;
debugk(DK_PCI,
"PCI(%d,%d,%d) configW(0x%x)=0x%x\n",
dev->busNo, dev->devNo, dev->funcNo, addr, data);
assert(! (addr & 3));
requestStatus = pciConfigOutLong(dev->busNo,
dev->devNo,
dev->funcNo,
(int) addr,
(UINT32) data);
return requestStatus;
}
VOID sysPciIoApicEnable
(
BOOL enable /* TRUE to enable, FALSE to disable */
)
{
#if defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3)
INT32 pciBusLpc = ICH2_LPC_PCI_BUSNO; /* bus# of ICH2/3 LPC */
INT32 pciDevLpc = ICH2_LPC_PCI_DEVNO; /* dev# of ICH2/3 LPC */
INT32 pciFuncLpc = ICH2_LPC_PCI_FUNCNO; /* func# of ICH2/3 LPC */
INT32 value; /* PCI config reg value */
UINT16 vendorId;
UINT16 deviceId;
/* is there ICH2 or ICH3? */
pciConfigInWord (pciBusLpc, pciDevLpc, pciFuncLpc,
PCI_CFG_VENDOR_ID, &vendorId);
pciConfigInWord (pciBusLpc, pciDevLpc, pciFuncLpc,
PCI_CFG_DEVICE_ID, &deviceId);
if (!(((vendorId == ICH2_LPC_VID) &&
((deviceId == ICH2_LPC_DID_S) || (deviceId == ICH2_LPC_DID_M))) ||
((vendorId == ICH3_LPC_VID) &&
((deviceId == ICH3_LPC_DID_S) || (deviceId == ICH3_LPC_DID_M)))))
return;
/* enables or disables 1) IOAPIC address decode 2) IO XAPIC extensions */
pciConfigInLong (pciBusLpc, pciDevLpc, pciFuncLpc,
ICH2_LPC_GEN_CNTL, &value);
if (enable)
value |= (ICH2_APICEN | ICH2_XAPIC_EN);
else
value &= ~(ICH2_APICEN | ICH2_XAPIC_EN);
pciConfigOutLong (pciBusLpc, pciDevLpc, pciFuncLpc,
ICH2_LPC_GEN_CNTL, value);
#endif /* defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3) */
}
END_OBJ *sysDec21x40EndLoad
(
char *pParamStr, /* ptr to initialization parameter string */
void *hwUnit /* Tulip unit number */
)
{
/*
* The format of the parameter string should be:
* "<unit number>:<device addr>:<PCI addr>:"
* "<ivec>:<ilevel>:<numRds>:<numTds>:<mem base>:<mem size>:"
* "<user flags>:<phyAddr>:<pPhyTbl>:<phyFlags>:<offset>"
*/
int unit = (int) hwUnit;
char *cp;
char paramStr [END_INIT_STR_MAX]; /* from end.h */
static char dec21x40ParamTemplate [] =
"%#x:0:%#x:0:-1:-1:-1:0:%#x::::2";
int busNo, deviceNo, funcNo;
UINT32 flags;
UINT32 csrAdrs;
UINT8 intLine;
UINT32 cfdd;
END_OBJ *pEnd;
if (strlen (pParamStr) == 0)
{
/*
* muxDevLoad() calls us twice. If the string is
* zero length, then this is the first time through
* this routine, so we just return.
*/
pEnd = dec21x40EndLoad (pParamStr);
}
else
{
if (pciFindDevice (VENDOR_ID_DEC, DEVICE_ID_21143, unit,
&busNo, &deviceNo, &funcNo) == OK)
{
flags = DEC_USR_21143;
}
else
if (pciFindDevice (VENDOR_ID_DEC, DEVICE_ID_21140, unit,
&busNo, &deviceNo, &funcNo) == OK)
{
flags = DEC_USR_21140;
}
else
if (pciFindDevice (VENDOR_ID_DEC, DEVICE_ID_21041, unit,
&busNo, &deviceNo, &funcNo) == OK)
{
flags = 0;
}
else
{
return (END_OBJ *)ERROR;
}
pciConfigInLong (busNo, deviceNo, funcNo, DEC_CFG_CBMA, &csrAdrs);
pciConfigInByte (busNo, deviceNo, funcNo, DEC_CFG_CFIT, &intLine);
/* Make sure that chip is out of sleep mode. */
pciConfigInLong (busNo, deviceNo, funcNo, DEC_CFG_CFDD, &cfdd);
pciConfigOutLong (busNo, deviceNo, funcNo, DEC_CFG_CFDD, 0);
pciConfigInLong (busNo, deviceNo, funcNo, DEC_CFG_CFDD, &cfdd);
/*
* On the second pass though here, we actually create
* the initialization parameter string on the fly.
* Note that we will be handed our unit number on the
* second pass through and we need to preserve that information.
* So we use the unit number handed from the input string.
*/
cp = strcpy (paramStr, pParamStr); /* cp points to paramStr */
/* Now, we advance cp, by finding the end the string */
cp += strlen (paramStr);
/* finish off the initialization parameter string */
flags |= DEC_USR_CAL_08 | DEC_USR_PBL_32 | DEC_USR_RML | DEC_USR_SF;
sprintf (cp, dec21x40ParamTemplate, csrAdrs, intLine, flags);
if ((pEnd = dec21x40EndLoad (paramStr)) == (END_OBJ *)ERROR)
{
printf ("Error: dec21x40 device failed EndLoad routine.\n");
}
}
return (pEnd);
}
int probe1()
{
unsigned int pciBusNo, pciDevNo, pciFuncNo;
unsigned char byte;
/* int i,j;*/
UINT32 s_pBA0, s_pBA1;
/* To ensure that taskDelay(1) is 1ms delay */
sysClkRateSet(1000);
if (pciConfigLibInit (PCI_MECHANISM_1, 0xCF8, 0xCFC, 0) != OK) {
printf("PCI lib config error\n");
return 1;
}
/****************************
* Find SoundCard
* Set BaseAddr0, BaseAddr1
****************************/
if(!(pciFindDevice(PCI_VENDOR_ID_CIRRUS,PCI_DEVICE_ID_CRYSTAL_CS4281,
0, &pciBusNo, &pciDevNo, &pciFuncNo)==OK)) {
printf("\n CS4281 sound card NOT FOUND!!! \n");
return 1;
}
printf("\n FOUND CS4281 sound card, configuring BA0,BA1... \n");
pciConfigOutLong( pciBusNo, pciDevNo, pciFuncNo,
PCI_CFG_BASE_ADDRESS_0, CS4281_pBA0);
/*
pciConfigOutLong( pciBusNo, pciDevNo, pciFuncNo,
PCI_CFG_BASE_ADDRESS_1, CS4281_pBA1);
*/
pciConfigInLong( pciBusNo, pciDevNo, pciFuncNo,
PCI_CFG_BASE_ADDRESS_0, &s_pBA0);
pciConfigInLong( pciBusNo, pciDevNo, pciFuncNo,
PCI_CFG_BASE_ADDRESS_1, &s_pBA1 );
printf ("\npBusNo pDeviceNo pFuncNo pBA0 pBA1\n\n");
printf ("%.8x %.8x %.8x %.8x %.8x \n",
pciBusNo, pciDevNo, pciFuncNo, s_pBA0,s_pBA1);
/********************************
* Config PCI Device Capability
* DMA Master
* MEM mapped
********************************/
/* Set the INTA vector */
pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo,
PCI_CFG_DEV_INT_LINE, &cs4281_irq);
printf("\nFound CS4281 configured for IRQ %d\n", cs4281_irq);
pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo,
PCI_CFG_DEV_INT_PIN, &byte);
printf("\tINT_PIN=%.8x\n", byte);
/* Enable the device's capabilities as specified
* Bus Master Enable/ Mem Space Enable */
pciConfigOutWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND,
(unsigned short)0x0006);
/***************************
* BringUp Hardware
***************************/
/*Include Init Function Here*/
cs4281_hw_init();
/****************************
* Allocate ADC_BUFFER
* Allocate DAC_BUFFER
*
* Hook cs4281_interrupt
*
* Program CoDec
****************************/
if((DAC_BUFFER=valloc(DAC_BUFFER_SIZE))==NULL) {
printf("\n DAC_BUFFER valloc failed!\n");
return 1;
}
memset( DAC_BUFFER, 0, DAC_BUFFER_SIZE );
printf("\ndac=%x",DAC_BUFFER);
/*for( i=0 ; i < DAC_BUFFER_SIZE ; i++ )
((char *)DAC_BUFFER)[i]=0x7f;*/
writel((UINT32)DAC_BUFFER+8,CS4281_pBA0 + BA0_DBA0);
writel(DAC_BUFFER_SIZE-16, CS4281_pBA0 + BA0_DBC0);
printf("\nbao=%x",readl(CS4281_pBA0 + BA0_DBA0));
printf("\nbco=%x",readl(CS4281_pBA0 + BA0_DBC0));
printf("\ncco=%x",readl(CS4281_pBA0 + BA0_DCC0));
if((ADC_BUFFER=valloc(ADC_BUFFER_SIZE))==NULL) {
printf("\n ADC_BUFFER valloc failed!\n");
return 1;
}
printf("\nadc=%x",ADC_BUFFER);
/*for( i=0 ; i < ADC_BUFFER_SIZE ; i++ )
((char *)ADC_BUFFER)[i]=0x7f;*/
writel((UINT32)ADC_BUFFER+8,CS4281_pBA0 + BA0_DBA1);
writel(ADC_BUFFER_SIZE-16, CS4281_pBA0 + BA0_DBC1);
/* connect interrupt */
printf("\n Hook cs4281_interrupt to vector %d\n",
(INUM_TO_IVEC (cs4281_irq+INT_NUM_IRQ0)));
pciIntConnect((INUM_TO_IVEC (cs4281_irq+INT_NUM_IRQ0)),
(VOIDFUNCPTR)cs4281_interrupt, 0);
sysIntEnablePIC(cs4281_irq);
SEM_DMA_Playback = semBCreate(SEM_Q_FIFO,SEM_EMPTY);
SEM_MY_Playback = semBCreate(SEM_Q_FIFO,SEM_EMPTY);
SEM_DMA_Record = semBCreate(SEM_Q_FIFO,SEM_EMPTY);
SEM_Sample = semBCreate(SEM_Q_FIFO,SEM_EMPTY);
CNT_DMA_Playback = CNT_DMA_Record = 0;
/* program coDec */
printf("\n Program CoDec (sample rate, DMA...)\n");
prog_codec();
/*********************************************
* start dac/adc, interrupt is comming...
*********************************************/
start_dac();
return 0;
}
void sysAic7880PciInit(void)
{
int busNo; /* PCI bus number */
int devNo; /* PCI device number */
int funcNo; /* PCI function number */
int index = 0; /* desired instance of device */
UINT32 membaseCsr; /* base address 0 */
UINT32 iobaseCsr; /* base address 1 */
char irq; /* IRQ level */
AIC7880_INFO *aicRes;
aicRes = &aic7880InfoTable;
if ((pciFindDevice (AIC7880_PCI_VENDOR_ID, AIC7880_PCI_DEVICE_ID,
index, &busNo, &devNo, &funcNo)) != OK)
{
logMsg("AIC 7880 SCSI controller not found\n", 0, 0, 0, 0, 0, 0);
return;
}
/* if PCI_CFG_FORCE is specified then set configuration parameters */
if (PCI_CFG_TYPE == PCI_CFG_FORCE)
{
pciConfigOutLong(busNo, devNo, funcNo, PCI_CFG_BASE_ADDRESS_0,
AIC7880_IOBASE);
pciConfigOutLong(busNo, devNo, funcNo, PCI_CFG_BASE_ADDRESS_1,
AIC7880_MEMBASE);
pciConfigOutByte(busNo, devNo, funcNo, PCI_CFG_DEV_INT_LINE,
AIC7880_INT_LVL);
}
/* read the configuration parameters */
pciConfigInLong(busNo, devNo, funcNo, PCI_CFG_BASE_ADDRESS_0,
&iobaseCsr);
pciConfigInLong(busNo, devNo, funcNo, PCI_CFG_BASE_ADDRESS_1,
&membaseCsr);
pciConfigInByte(busNo, devNo, funcNo, PCI_CFG_DEV_INT_LINE,
&irq);
membaseCsr &= PCI_MEMBASE_MASK;
iobaseCsr &= PCI_IOBASE_MASK;
/* update the mmu table */
if (sysMmuMapAdd((void *)membaseCsr, (UINT)AIC7880_MEMSIZE,
(UINT)AIC7880_INIT_STATE_MASK,
(UINT)AIC7880_INIT_STATE) == ERROR)
{
logMsg("Unable map requested memory\n", 0, 0, 0, 0, 0, 0);
return;
}
/* update the device specific info */
aicRes->pciBus = busNo;
aicRes->pciDevice = devNo;
aicRes->pciFunc = funcNo;
aicRes->irq = irq;
/* enable mapped memory and IO addresses */
pciConfigOutWord (aicRes->pciBus, aicRes->pciDevice, aicRes->pciFunc,
PCI_CFG_COMMAND, PCI_CMD_IO_ENABLE |
PCI_CMD_MEM_ENABLE | PCI_CMD_MASTER_ENABLE);
}
void
osl_pci_write_config(pciinfo_t *pciinfo, uint offset, uint size, uint val)
{
ASSERT(size == 4);
pciConfigOutLong(pciinfo->bus, pciinfo->dev, pciinfo->func, offset, val);
}
