void mpcpcibrattach(struct device *parent, struct device *self, void *aux) { struct pcibr_softc *sc = (struct pcibr_softc *)self; struct confargs *ca = aux; struct pcibr_config *lcp; struct pcibus_attach_args pba; int node; int of_node = 0; char compat[32]; u_int32_t addr_offset; u_int32_t data_offset; int i; int len; int rangesize; u_int32_t range_store[32]; if (ca->ca_node == 0) { printf("invalid node on mpcpcibr config\n"); return; } len=OF_getprop(ca->ca_node, "name", compat, sizeof (compat)); compat[len] = '\0'; if (len > 0) printf(" %s", compat); len=OF_getprop(ca->ca_node, "compatible", compat, sizeof (compat)); if (len <= 0 ) { len=OF_getprop(ca->ca_node, "name", compat, sizeof (compat)); if (len <= 0) { printf(" compatible and name not found\n"); return; } compat[len] = 0; if (strcmp (compat, "bandit") != 0) { printf(" compatible not found and name %s found\n", compat); return; } } compat[len] = 0; if ((rangesize = OF_getprop(ca->ca_node, "ranges", range_store, sizeof (range_store))) <= 0) { if (strcmp(compat, "u3-ht") == 0) { range_store[0] = 0xabb10113; /* appl U3; */ } else printf("range lookup failed, node %x\n", ca->ca_node); } /* translate byte(s) into item count*/ lcp = sc->sc_pcibr = &sc->pcibr_config; if (ppc_proc_is_64b) mpcpcibus_find_ranges_64 (sc, range_store, rangesize); else mpcpcibus_find_ranges_32 (sc, range_store, rangesize); addr_offset = 0; for (i = 0; config_offsets[i].compat != NULL; i++) { struct config_type *co = &config_offsets[i]; if (strcmp(co->compat, compat) == 0) { addr_offset = co->addr; data_offset = co->data; lcp->config_type = co->config_type; break; } } if (addr_offset == 0) { printf("unable to find match for" " compatible %s\n", compat); return; } #ifdef DEBUG_FIXUP printf(" mem base %x sz %x io base %x sz %x\n" " config addr %x config data %x\n", sc->sc_membus_space.bus_base, sc->sc_membus_space.bus_size, sc->sc_iobus_space.bus_base, sc->sc_iobus_space.bus_size, addr_offset, data_offset); #endif if ( bus_space_map(&(sc->sc_iobus_space), addr_offset, NBPG, 0, &lcp->ioh_cf8) != 0 ) panic("mpcpcibus: unable to map self"); if ( bus_space_map(&(sc->sc_iobus_space), data_offset, NBPG, 0, &lcp->ioh_cfc) != 0 ) panic("mpcpcibus: unable to map self"); of_node = ca->ca_node; lcp->node = ca->ca_node; lcp->lc_pc.pc_conf_v = lcp; lcp->lc_pc.pc_attach_hook = mpc_attach_hook; lcp->lc_pc.pc_bus_maxdevs = mpc_bus_maxdevs; lcp->lc_pc.pc_make_tag = mpc_make_tag; lcp->lc_pc.pc_decompose_tag = mpc_decompose_tag; lcp->lc_pc.pc_conf_read = mpc_conf_read; lcp->lc_pc.pc_conf_write = mpc_conf_write; lcp->lc_pc.pc_ether_hw_addr = of_ether_hw_addr; lcp->lc_iot = &sc->sc_iobus_space; lcp->lc_memt = &sc->sc_membus_space; lcp->lc_pc.pc_intr_v = lcp; lcp->lc_pc.pc_intr_map = mpc_intr_map; lcp->lc_pc.pc_intr_string = mpc_intr_string; lcp->lc_pc.pc_intr_line = mpc_intr_line; lcp->lc_pc.pc_intr_establish = mpc_intr_establish; lcp->lc_pc.pc_intr_disestablish = mpc_intr_disestablish; printf(": %s, Revision 0x%x\n", compat, mpc_cfg_read_1(lcp, MPC106_PCI_REVID)); if ((strcmp(compat, "bandit")) != 0) pci_addr_fixup(sc, &lcp->lc_pc, 32); pba.pba_dmat = &pci_bus_dma_tag; pba.pba_busname = "pci"; pba.pba_iot = &sc->sc_iobus_space; pba.pba_memt = &sc->sc_membus_space; pba.pba_pc = &lcp->lc_pc; pba.pba_domain = pci_ndomains++; pba.pba_bus = 0; pba.pba_bridgetag = NULL; /* we want to check pci irq settings */ if (of_node != 0) { int nn; for (node = OF_child(of_node); node; node = nn) { char name[32]; int len; len = OF_getprop(node, "name", name, sizeof(name)); name[len] = 0; fix_node_irq(node, &pba); /* iterate section */ if ((nn = OF_child(node)) != 0) continue; while ((nn = OF_peer(node)) == 0) { node = OF_parent(node); if (node == of_node) { nn = 0; /* done */ break; } } } } config_found(self, &pba, mpcpcibrprint); }
/* * Attach the mainbus. */ void mainbus_attach(device_t parent, device_t self, void *aux) { union mainbus_attach_args mba; #if defined(DOM0OPS) && defined(XEN3) int numcpus = 0; #ifdef MPBIOS int mpbios_present = 0; #endif #if NACPI > 0 || defined(MPBIOS) int numioapics = 0; #endif #endif /* defined(DOM0OPS) && defined(XEN3) */ aprint_naive("\n"); aprint_normal("\n"); #ifndef XEN3 memset(&mba.mba_caa, 0, sizeof(mba.mba_caa)); mba.mba_caa.cpu_number = 0; mba.mba_caa.cpu_role = CPU_ROLE_SP; mba.mba_caa.cpu_func = 0; config_found_ia(self, "cpubus", &mba.mba_caa, mainbus_print); #else /* XEN3 */ #ifdef DOM0OPS if (xendomain_is_dom0()) { #ifdef MPBIOS mpbios_present = mpbios_probe(self); #endif #if NPCI > 0 /* ACPI needs to be able to access PCI configuration space. */ pci_mode = pci_mode_detect(); #ifdef PCI_BUS_FIXUP pci_maxbus = pci_bus_fixup(NULL, 0); aprint_debug_dev(self, "PCI bus max, after pci_bus_fixup: %i\n", pci_maxbus); #ifdef PCI_ADDR_FIXUP pciaddr.extent_port = NULL; pciaddr.extent_mem = NULL; pci_addr_fixup(NULL, pci_maxbus); #endif /* PCI_ADDR_FIXUP */ #endif /* PCI_BUS_FIXUP */ #if NACPI > 0 acpi_present = acpi_probe(); if (acpi_present) mpacpi_active = mpacpi_scan_apics(self, &numcpus, &numioapics); if (!mpacpi_active) #endif { #ifdef MPBIOS if (mpbios_present) mpbios_scan(self, &numcpus, &numioapics); else #endif if (numcpus == 0) { memset(&mba.mba_caa, 0, sizeof(mba.mba_caa)); mba.mba_caa.cpu_number = 0; mba.mba_caa.cpu_role = CPU_ROLE_SP; mba.mba_caa.cpu_func = 0; config_found_ia(self, "cpubus", &mba.mba_caa, mainbus_print); } } #if NIOAPIC > 0 ioapic_enable(); #endif #endif /* NPCI */ } #endif /* DOM0OPS */ #endif /* XEN3 */ #if NIPMI > 0 memset(&mba.mba_ipmi, 0, sizeof(mba.mba_ipmi)); mba.mba_ipmi.iaa_iot = X86_BUS_SPACE_IO; mba.mba_ipmi.iaa_memt = X86_BUS_SPACE_MEM; if (ipmi_probe(&mba.mba_ipmi)) config_found_ia(self, "ipmibus", &mba.mba_ipmi, 0); #endif #if NHYPERVISOR > 0 mba.mba_haa.haa_busname = "hypervisor"; config_found_ia(self, "hypervisorbus", &mba.mba_haa, mainbus_print); #endif }
/* * Attach the mainbus. */ void mainbus_attach(device_t parent, device_t self, void *aux) { #if NPCI > 0 union mainbus_attach_args mba; #endif #if NACPI > 0 int acpi_present = 0; #endif #ifdef MPBIOS int mpbios_present = 0; #endif int mpacpi_active = 0; int numcpus = 0; #if NACPI > 0 || defined(MPBIOS) int numioapics = 0; #endif #if defined(PCI_BUS_FIXUP) int pci_maxbus = 0; #endif aprint_naive("\n"); aprint_normal("\n"); #ifdef MPBIOS mpbios_present = mpbios_probe(self); #endif #if NPCI > 0 pci_mode = pci_mode_detect(); #if defined(PCI_BUS_FIXUP) if (pci_mode != 0) { pci_maxbus = pci_bus_fixup(NULL, 0); aprint_debug("PCI bus max, after pci_bus_fixup: %i\n", pci_maxbus); #if defined(PCI_ADDR_FIXUP) pciaddr.extent_port = NULL; pciaddr.extent_mem = NULL; pci_addr_fixup(NULL, pci_maxbus); #endif } #endif #endif #if NACPI > 0 if ((boothowto & RB_MD2) == 0 && acpi_check(self, "acpibus")) acpi_present = acpi_probe(); /* * First, see if the MADT contains CPUs, and possibly I/O APICs. * Building the interrupt routing structures can only * be done later (via a callback). */ if (acpi_present) mpacpi_active = mpacpi_scan_apics(self, &numcpus, &numioapics); #endif if (!mpacpi_active) { #ifdef MPBIOS if (mpbios_present) mpbios_scan(self, &numcpus, &numioapics); else #endif if (numcpus == 0) { struct cpu_attach_args caa; memset(&caa, 0, sizeof(caa)); caa.cpu_number = 0; caa.cpu_role = CPU_ROLE_SP; caa.cpu_func = 0; config_found_ia(self, "cpubus", &caa, mainbus_print); } } #if NISADMA > 0 && NACPI > 0 /* * ACPI needs ISA DMA initialized before they start probing. */ isa_dmainit(&x86_isa_chipset, X86_BUS_SPACE_IO, &isa_bus_dma_tag, self); #endif #if NACPI > 0 if (acpi_present) { mba.mba_acpi.aa_iot = X86_BUS_SPACE_IO; mba.mba_acpi.aa_memt = X86_BUS_SPACE_MEM; mba.mba_acpi.aa_pc = NULL; mba.mba_acpi.aa_pciflags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; mba.mba_acpi.aa_ic = &x86_isa_chipset; config_found_ia(self, "acpibus", &mba.mba_acpi, 0); } #endif #if NIPMI > 0 memset(&mba.mba_ipmi, 0, sizeof(mba.mba_ipmi)); mba.mba_ipmi.iaa_iot = X86_BUS_SPACE_IO; mba.mba_ipmi.iaa_memt = X86_BUS_SPACE_MEM; if (ipmi_probe(&mba.mba_ipmi)) config_found_ia(self, "ipmibus", &mba.mba_ipmi, 0); #endif #if NPCI > 0 if (pci_mode != 0) { mba.mba_pba.pba_iot = X86_BUS_SPACE_IO; mba.mba_pba.pba_memt = X86_BUS_SPACE_MEM; mba.mba_pba.pba_dmat = &pci_bus_dma_tag; mba.mba_pba.pba_dmat64 = &pci_bus_dma64_tag; mba.mba_pba.pba_pc = NULL; mba.mba_pba.pba_flags = pci_bus_flags(); mba.mba_pba.pba_bus = 0; mba.mba_pba.pba_bridgetag = NULL; #if NACPI > 0 && defined(ACPI_SCANPCI) if (mpacpi_active) mpacpi_scan_pci(self, &mba.mba_pba, pcibusprint); else #endif #if defined(MPBIOS) && defined(MPBIOS_SCANPCI) if (mpbios_scanned != 0) mpbios_scan_pci(self, &mba.mba_pba, pcibusprint); else #endif config_found_ia(self, "pcibus", &mba.mba_pba, pcibusprint); #if NACPI > 0 if (mp_verbose) acpi_pci_link_state(); #endif } #endif #if NISA > 0 if (isa_has_been_seen == 0) config_found_ia(self, "isabus", &mba_iba, isabusprint); #endif if (!pmf_device_register(self, NULL, NULL)) aprint_error_dev(self, "couldn't establish power handler\n"); }