ACPI_STATUS
AcpiOsReadPciConfiguration (
ACPI_PCI_ID *PciId,
UINT32 Register,
void *Value,
UINT32 Width)
{
u_int32_t byte_width = Width / 8;
u_int32_t val;
if (!pci_cfgregopen())
return(AE_NOT_EXIST);
val = pci_cfgregread(PciId->Bus, PciId->Device, PciId->Function, Register, byte_width);
switch (Width) {
case 8:
*(u_int8_t *)Value = val & 0xff;
break;
case 16:
*(u_int16_t *)Value = val & 0xffff;
break;
case 32:
*(u_int32_t *)Value = val;
break;
default:
/* debug trap goes here */
break;
}
return(AE_OK);
}
static int
mptable_hostb_probe(device_t dev)
{
if (pci_cfgregopen() == 0)
return (ENXIO);
if (mptable_pci_probe_table(pcib_get_bus(dev)) != 0)
return (ENXIO);
device_set_desc(dev, "MPTable Host-PCI bridge");
return (0);
}
static int
acpi_pcib_acpi_probe(device_t dev)
{
static char *pcib_ids[] = { "PNP0A03", NULL };
if (acpi_disabled("pcib") ||
ACPI_ID_PROBE(device_get_parent(dev), dev, pcib_ids) == NULL)
return (ENXIO);
if (pci_cfgregopen() == 0)
return (ENXIO);
device_set_desc(dev, "ACPI Host-PCI bridge");
return (0);
}
ACPI_STATUS
AcpiOsWritePciConfiguration(ACPI_PCI_ID *PciId, UINT32 Register,
UINT64 Value, UINT32 Width)
{
if (Width == 64)
return (AE_SUPPORT);
if (!pci_cfgregopen())
return (AE_NOT_EXIST);
pci_cfgregwrite(PciId->Bus, PciId->Device, PciId->Function, Register,
(uint32_t)Value, Width / 8); /* XXX casting */
return (AE_OK);
}
ACPI_STATUS
AcpiOsWritePciConfiguration (
ACPI_PCI_ID *PciId,
UINT32 Register,
ACPI_INTEGER Value,
UINT32 Width)
{
u_int32_t byte_width = Width / 8;
if (!pci_cfgregopen())
return(AE_NOT_EXIST);
pci_cfgregwrite(PciId->Bus, PciId->Device, PciId->Function, Register, Value, byte_width);
return(AE_OK);
}
static int
mptable_hostb_probe(device_t dev)
{
if (!ioapic_enable)
return (ENXIO);
if (pci_cfgregopen() == 0)
return (ENXIO);
#ifdef notyet
if (mptable_pci_probe_table(pcib_get_bus(dev)) != 0)
return (ENXIO);
#endif
device_set_desc(dev, "MPTABLE Host-PCI bridge");
return (0);
}
static int
acpi_pcib_pci_probe(device_t dev)
{
if (pci_get_class(dev) != PCIC_BRIDGE ||
pci_get_subclass(dev) != PCIS_BRIDGE_PCI ||
acpi_disabled("pci"))
return (ENXIO);
if (acpi_get_handle(dev) == NULL)
return (ENXIO);
if (pci_cfgregopen() == 0)
return (ENXIO);
device_set_desc(dev, "ACPI PCI-PCI bridge");
return (-1000);
}
int
pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
{
if (bootverbose) {
kprintf("PCIe: Memory Mapped configuration base @ 0x%jx, "
"bus [%d, %d]\n", (uintmax_t)base, minbus, maxbus);
}
if (!mcfg_enable)
return 0;
if (minbus != 0)
return 0;
if (bootverbose)
kprintf("PCIe: Using Memory Mapped configuration\n");
pcie_base = (vm_offset_t)pmap_mapdev_uncacheable(base,
((unsigned)maxbus + 1) << 20);
pcie_minbus = minbus;
pcie_maxbus = maxbus;
cfgmech = CFGMECH_PCIE;
/*
* On some AMD systems, some of the devices on bus 0 are
* inaccessible using memory-mapped PCI config access. Walk
* bus 0 looking for such devices. For these devices, we will
* fall back to using type 1 config access instead.
*/
if (pci_cfgregopen() != 0) {
int slot;
for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
uint32_t val1, val2;
val1 = pcireg_cfgread(0, slot, 0, 0, 4);
if (val1 == 0xffffffff)
continue;
val2 = pciereg_cfgread(0, slot, 0, 0, 4);
if (val2 != val1)
pcie_badslots |= (1 << slot);
}
}
return 1;
}
int
acpi_pcib_probe(device_t dev)
{
/*
* Don't attach if we're not really there.
*
* XXX: This isn't entirely correct since we may be a PCI bus
* on a hot-plug docking station, etc.
*/
if (!acpi_DeviceIsPresent(dev))
return ENXIO;
if (pci_cfgregopen() == 0)
return ENXIO;
return 0;
}
ACPI_STATUS
AcpiOsReadPciConfiguration(ACPI_PCI_ID *PciId, UINT32 Register, UINT64 *Value,
UINT32 Width)
{
int bytes = Width / 8;
if (Width == 64)
return (AE_SUPPORT);
if (!pci_cfgregopen())
return (AE_NOT_EXIST);
*Value = pci_cfgregread(PciId->Bus, PciId->Device,
PciId->Function, Register, bytes);
*Value &= (1 << (bytes * 8)) - 1;
return (AE_OK);
}
static void
qpi_identify(driver_t *driver, device_t parent)
{
/* Check CPUID to ensure this is an i7 CPU of some sort. */
if (!(cpu_vendor_id == CPU_VENDOR_INTEL &&
CPUID_TO_FAMILY(cpu_id) == 0x6 &&
(CPUID_TO_MODEL(cpu_id) == 0x1a || CPUID_TO_MODEL(cpu_id) == 0x2c)))
return;
/* PCI config register access is required. */
if (pci_cfgregopen() == 0)
return;
/* Add a qpi bus device. */
if (BUS_ADD_CHILD(parent, 20, "qpi", -1) == NULL)
panic("Failed to add qpi bus");
}
static int
acpi_pcib_acpi_probe(device_t dev)
{
if ((acpi_get_type(dev) == ACPI_TYPE_DEVICE) &&
!acpi_disabled("pci") &&
acpi_MatchHid(dev, "PNP0A03")) {
if (!pci_cfgregopen())
return(ENXIO);
/*
* Set device description
*/
device_set_desc(dev, "ACPI Host-PCI bridge");
return(0);
}
return(ENXIO);
}
int
pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
{
uint32_t val1, val2;
int slot;
if (!mcfg_enable)
return (0);
if (minbus != 0)
return (0);
if (bootverbose)
printf("PCIe: Memory Mapped configuration base @ 0x%lx\n",
base);
/* XXX: We should make sure this really fits into the direct map. */
pcie_base = (vm_offset_t)pmap_mapdev(base, (maxbus + 1) << 20);
pcie_minbus = minbus;
pcie_maxbus = maxbus;
cfgmech = CFGMECH_PCIE;
/*
* On some AMD systems, some of the devices on bus 0 are
* inaccessible using memory-mapped PCI config access. Walk
* bus 0 looking for such devices. For these devices, we will
* fall back to using type 1 config access instead.
*/
if (pci_cfgregopen() != 0) {
for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
val1 = pcireg_cfgread(0, slot, 0, 0, 4);
if (val1 == 0xffffffff)
continue;
val2 = pciereg_cfgread(0, slot, 0, 0, 4);
if (val2 != val1)
pcie_badslots |= (1 << slot);
}
}
return (1);
}
ACPI_STATUS
AcpiOsReadPciConfiguration(ACPI_PCI_ID *PciId, UINT32 Register, UINT64 *Value,
UINT32 Width)
{
#ifdef __aarch64__
/* ARM64TODO: Add pci support */
return (AE_SUPPORT);
#else
if (Width == 64)
return (AE_SUPPORT);
if (!pci_cfgregopen())
return (AE_NOT_EXIST);
*(UINT64 *)Value = pci_cfgregread(PciId->Bus, PciId->Device,
PciId->Function, Register, Width / 8);
return (AE_OK);
#endif
}