void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id) { struct PCIDevice *bridge_dev; int i, num; uint16_t pch_dev_id = 0xffff; uint8_t pch_rev_id; num = ARRAY_SIZE(igd_combo_id_infos); for (i = 0; i < num; i++) { if (gpu_dev_id == igd_combo_id_infos[i].gpu_device_id) { pch_dev_id = igd_combo_id_infos[i].pch_device_id; pch_rev_id = igd_combo_id_infos[i].pch_revision_id; } } if (pch_dev_id == 0xffff) { return; } /* Currently IGD drivers always need to access PCH by 1f.0. */ bridge_dev = pci_create_simple(bus, PCI_DEVFN(0x1f, 0), "igd-passthrough-isa-bridge"); /* * Note that vendor id is always PCI_VENDOR_ID_INTEL. */ if (!bridge_dev) { fprintf(stderr, "set igd-passthrough-isa-bridge failed!\n"); return; } pci_config_set_device_id(bridge_dev->config, pch_dev_id); pci_config_set_revision(bridge_dev->config, pch_rev_id); }
/* via ide func */ static int vt82c686b_ide_initfn(PCIDevice *dev) { PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);; uint8_t *pci_conf = d->dev.config; pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_IDE); pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */ pci_config_set_revision(pci_conf,0x06); /* Revision 0.6 */ pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); qemu_register_reset(via_reset, d); pci_register_bar((PCIDevice *)d, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, bmdma_map); vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d); ide_bus_new(&d->bus[0], &d->dev.qdev); ide_bus_new(&d->bus[1], &d->dev.qdev); ide_init2(&d->bus[0], isa_reserve_irq(14)); ide_init2(&d->bus[1], isa_reserve_irq(15)); ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6); ide_init_ioport(&d->bus[1], 0x170, 0x376); return 0; }