uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len) { uint32_t val; assert(pci_dev->devfn == 0x00); if ( !igd_passthru ) { return pci_default_read_config(pci_dev, config_addr, len); } switch (config_addr) { case 0x00: /* vendor id */ case 0x02: /* device id */ case 0x52: /* processor graphics control register */ case 0xa0: /* top of memory */ case 0xb0: /* ILK: BSM: should read from dev 2 offset 0x5c */ case 0x58: /* SNB: PAVPC Offset */ case 0xa4: /* SNB: graphics base of stolen memory */ case 0xa8: /* SNB: base of GTT stolen memory */ val = pt_pci_host_read(0, PCI_SLOT(pci_dev->devfn), 0, config_addr, len); PT_LOG("pci_config_read: %x:%x.%x: addr=%x len=%x val=%x\n", pci_bus_num(pci_dev->bus), PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn), config_addr, len, val); break; default: val = pci_default_read_config(pci_dev, config_addr, len); } return val; }
static uint32_t xilinx_pcie_root_config_read(PCIDevice *d, uint32_t address, int len) { XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent); uint32_t val; switch (address) { case ROOTCFG_INTDEC: val = s->intr; break; case ROOTCFG_INTMASK: val = s->intr_mask; break; case ROOTCFG_PSCR: val = s->link_up ? ROOTCFG_PSCR_LINK_UP : 0; break; case ROOTCFG_RPSCR: if (s->intr_fifo_r != s->intr_fifo_w) { s->rpscr &= ~ROOTCFG_RPSCR_INTNEMPTY; } else { s->rpscr |= ROOTCFG_RPSCR_INTNEMPTY; } val = s->rpscr; break; case ROOTCFG_RPIFR1: if (s->intr_fifo_w == s->intr_fifo_r) { /* FIFO empty */ val = 0; } else { val = s->intr_fifo[s->intr_fifo_r].fifo_reg1; } break; case ROOTCFG_RPIFR2: if (s->intr_fifo_w == s->intr_fifo_r) { /* FIFO empty */ val = 0; } else { val = s->intr_fifo[s->intr_fifo_r].fifo_reg2; } break; default: val = pci_default_read_config(d, address, len); break; } return val; }
static uint32_t assigned_dev_pci_read_config(PCIDevice *d, uint32_t address, int len) { uint32_t val = 0; int fd; ssize_t ret; AssignedDevice *pci_dev = container_of(d, AssignedDevice, dev); if (address < 0x4 || (pci_dev->need_emulate_cmd && address == 0x4) || (address >= 0x10 && address <= 0x24) || address == 0x34 || address == 0x3c || address == 0x3d || pci_access_cap_config(d, address, len)) { val = pci_default_read_config(d, address, len); DEBUG("(%x.%x): address=%04x val=0x%08x len=%d\n", (d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val, len); return val; }
static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len) { I6300State *d = DO_UPCAST(I6300State, dev, dev); uint32_t data; i6300esb_debug ("addr = %x, len = %d\n", addr, len); if (addr == ESB_CONFIG_REG && len == 2) { data = (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) | (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) | d->int_type; return data; } else if (addr == ESB_LOCK_REG && len == 1) { data = (d->free_run ? ESB_WDT_FUNC : 0) | (d->locked ? ESB_WDT_LOCK : 0) | (d->enabled ? ESB_WDT_ENABLE : 0); return data; } else { return pci_default_read_config(dev, addr, len); } }