static int
pci_device_freebsd_probe( struct pci_device * dev )
{
struct pci_device_private *priv = (struct pci_device_private *) dev;
uint32_t reg, size;
uint8_t irq;
int err, i, bar;
/* Many of the fields were filled in during initial device enumeration.
* At this point, we need to fill in regions, rom_size, and irq.
*/
err = pci_device_cfg_read_u8( dev, &irq, 60 );
if (err)
return errno;
dev->irq = irq;
bar = 0x10;
for (i = 0; i < pci_device_freebsd_get_num_regions( dev ); i++) {
pci_device_freebsd_get_region_info( dev, i, bar );
if (dev->regions[i].is_64) {
bar += 0x08;
i++;
} else
bar += 0x04;
}
/* If it's a VGA device, set up the rom size for read_rom */
if ((dev->device_class & 0x00ffff00) ==
((PCIC_DISPLAY << 16) | (PCIS_DISPLAY_VGA << 8)))
{
err = pci_device_cfg_read_u32( dev, ®, PCIR_BIOS );
if (err)
return errno;
if (reg == 0) {
dev->rom_size = 0x10000;
return 0;
}
err = pci_device_cfg_write_u32( dev, ~PCIM_BIOS_ENABLE, PCIR_BIOS );
if (err)
return errno;
pci_device_cfg_read_u32( dev, &size, PCIR_BIOS );
pci_device_cfg_write_u32( dev, reg, PCIR_BIOS );
if ((reg & PCIM_BIOS_ADDR_MASK) != 0) {
priv->rom_base = (reg & PCIM_BIOS_ADDR_MASK);
dev->rom_size = -(size & PCIM_BIOS_ADDR_MASK);
}
}
return 0;
}
static int
pci_device_freebsd_probe( struct pci_device * dev )
{
struct pci_device_private *priv = (struct pci_device_private *) dev;
struct pci_bar_io bar;
uint8_t irq;
int err, i;
#if HAVE_PCI_IO_PC_DOMAIN
bar.pbi_sel.pc_domain = dev->domain;
#endif
bar.pbi_sel.pc_bus = dev->bus;
bar.pbi_sel.pc_dev = dev->dev;
bar.pbi_sel.pc_func = dev->func;
/* Many of the fields were filled in during initial device enumeration.
* At this point, we need to fill in regions, rom_size, and irq.
*/
err = pci_device_cfg_read_u8( dev, &irq, 60 );
if (err)
return errno;
dev->irq = irq;
for (i = 0; i < pci_device_freebsd_get_num_regions( dev ); i++) {
bar.pbi_reg = PCIR_BAR(i);
if ( ioctl( freebsd_pci_sys->pcidev, PCIOCGETBAR, &bar ) < 0 )
continue;
if (PCI_BAR_IO(bar.pbi_base))
dev->regions[i].is_IO = 1;
if ((bar.pbi_base & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64)
dev->regions[i].is_64 = 1;
if (bar.pbi_base & PCIM_BAR_MEM_PREFETCH)
dev->regions[i].is_prefetchable = 1;
dev->regions[i].base_addr = bar.pbi_base & ~((uint64_t)0xf);
dev->regions[i].size = bar.pbi_length;
}
/* If it's a VGA device, set up the rom size for read_rom using the
* 0xc0000 mapping.
*/
if ((dev->device_class & 0x00ffff00) ==
((PCIC_DISPLAY << 16) | (PCIS_DISPLAY_VGA << 8))) {
dev->rom_size = 64 * 1024;
}
return 0;
}
int main(int argc, char **argv)
{
struct pci_device *dev, *bridge;
int error;
uint8_t stepping;
const char *step_desc = "??";
error = pci_system_init();
if (error != 0) {
fprintf(stderr, "Couldn't initialize PCI system: %s\n",
strerror(error));
exit(1);
}
/* Grab the graphics card */
dev = pci_device_find_by_slot(0, 0, 2, 0);
if (dev == NULL)
errx(1, "Couldn't find graphics card");
error = pci_device_probe(dev);
if (error != 0) {
fprintf(stderr, "Couldn't probe graphics card: %s\n",
strerror(error));
exit(1);
}
if (dev->vendor_id != 0x8086)
errx(1, "Graphics card is non-intel");
bridge = pci_device_find_by_slot(0, 0, 0, 0);
if (dev == NULL)
errx(1, "Couldn't bridge");
error = pci_device_cfg_read_u8(bridge, &stepping, 8);
if (error != 0) {
fprintf(stderr, "Couldn't read revision ID: %s\n",
strerror(error));
exit(1);
}
switch (dev->device_id) {
case PCI_CHIP_I915_G:
if (stepping < 0x04)
step_desc = "<B1";
else if (stepping == 0x04)
step_desc = "B1";
else if (stepping == 0x0e)
step_desc = "C2";
else if (stepping > 0x0e)
step_desc = ">C2";
else
step_desc = ">B1 <C2";
break;
case PCI_CHIP_I915_GM:
if (stepping < 0x03)
step_desc = "<B1";
else if (stepping == 0x03)
step_desc = "B1/C0";
else if (stepping == 0x04)
step_desc = "C1/C2";
else
step_desc = ">C2";
break;
case PCI_CHIP_I945_GM:
if (stepping < 0x03)
step_desc = "<A3";
else if (stepping == 0x03)
step_desc = "A3";
else
step_desc = ">A3";
break;
case PCI_CHIP_I965_G:
case PCI_CHIP_I965_Q:
if (stepping < 0x02)
step_desc = "<C1";
else if (stepping == 0x02)
step_desc = "C1/C2";
else
step_desc = ">C2";
break;
case PCI_CHIP_I965_GM:
if (stepping < 0x03)
step_desc = "<C0";
else if (stepping == 0x03)
step_desc = "C0";
else
step_desc = ">C0";
break;
case PCI_CHIP_I965_G_1:
if (stepping < 0x03)
step_desc = "<E0";
else if (stepping == 0x03)
step_desc = "E0";
else
step_desc = ">E0";
break;
case PCI_CHIP_GM45_GM:
if (stepping < 0x07)
step_desc = "<B3";
else if (stepping == 0x03)
step_desc = "B3";
else
step_desc = ">B3";
break;
case PCI_CHIP_G45_G:
case PCI_CHIP_Q45_G:
case PCI_CHIP_G41_G:
if (stepping < 0x02)
step_desc = "<A2";
else if (stepping == 0x02)
step_desc = "A2";
else if (stepping == 0x03)
step_desc = "A3";
else
step_desc = ">A3";
break;
}
printf("Vendor: 0x%04x, Device: 0x%04x, Revision: 0x%02x (%s)\n",
dev->vendor_id,
dev->device_id,
stepping,
step_desc);
print_clock_info(dev);
return 0;
}
static void get_device_serial_number(struct pci_device *dev,
struct hba_info *info)
{
uint32_t pcie_cap_header;
uint32_t dword_high = 0;
uint32_t dword_low = 0;
uint16_t pcie_cap_id;
pciaddr_t offset;
uint16_t status;
uint8_t cap_ptr;
int rc;
/* Default */
snprintf(info->serial_number, sizeof(info->serial_number), "Unknown");
/*
* Read the Status Regiser in the PCIe configuration
* header space to see if the PCI Capability List is
* supported by this device.
*/
rc = pci_device_cfg_read_u16(dev, &status, PCI_STATUS);
if (rc) {
fprintf(stderr, "Failed reading PCI status register\n");
return;
}
if (!(status & PCI_STATUS_CAP_LIST)) {
fprintf(stderr, "PCI capabilities are not supported\n");
return;
}
/*
* Read the offset (cap_ptr) of first entry in the capability list in
* the PCI configuration space.
*/
rc = pci_device_cfg_read_u8(dev, &cap_ptr, PCI_CAPABILITY_LIST);
if (rc) {
fprintf(stderr,
"Failed reading PCI Capability List Register\n");
return;
}
offset = cap_ptr;
/* Search for the PCIe capability */
while (offset) {
uint8_t next_cap;
uint8_t cap_id;
rc = pci_device_cfg_read_u8(dev, &cap_id,
offset + PCI_CAP_LIST_ID);
if (rc) {
fprintf(stderr,
"Failed reading capability ID at 0x%"PRIx64"\n",
offset + PCI_CAP_LIST_ID);
return;
}
if (cap_id != PCI_CAP_ID_EXP) {
rc = pci_device_cfg_read_u8(dev, &next_cap,
offset + PCI_CAP_LIST_NEXT);
if (rc) {
fprintf(stderr,
"Failed reading next capability ID at 0x%"PRIx64"\n",
offset + PCI_CAP_LIST_NEXT);
return;
}
offset = (pciaddr_t) next_cap;
continue;
}
/*
* PCIe Capability Structure exists!
*/
/*
* The first PCIe extended capability is located at
* offset 0x100 in the device configuration space.
*/
offset = 0x100;
do {
rc = pci_device_cfg_read_u32(dev, &pcie_cap_header,
offset);
if (rc) {
fprintf(stderr,
"Failed reading PCIe config header\n");
return;
}
/* Get the PCIe Extended Capability ID */
pcie_cap_id = pcie_cap_header & 0xffff;
if (pcie_cap_id != PCI_EXT_CAP_ID_DSN) {
/* Get the offset of the next capability */
offset = (pciaddr_t) pcie_cap_header >> 20;
continue;
}
/*
* Found the serial number register!
*/
(void) pci_device_cfg_read_u32(dev, &dword_low,
offset + 4);
(void) pci_device_cfg_read_u32(dev, &dword_high,
offset + 8);
snprintf(info->serial_number,
sizeof(info->serial_number),
"%02X%02X%02X%02X%02X%02X\n",
dword_high >> 24, (dword_high >> 16) & 0xff,
(dword_high >> 8) & 0xff,
(dword_low >> 16) & 0xff,
(dword_low >> 8) & 0xff, dword_low & 0xff);
break;
} while (offset);
break;
}
uint8_t getBrightness( struct pci_device * dev ) {
uint8_t val;
pci_device_cfg_read_u8( dev, &val, 0xf4 );
return val;
}
