static void __init pci_fixup_isp1020(struct pci_dev *d) { unsigned short command; d->resource[0].start |= ((unsigned long)(bus_to_nid[d->bus->number])<<32); printk("PCI: Fixing isp1020 in [bus:slot.fn] %s\n", d->slot_name); /* * Configure device to allow bus mastering, i/o and memory mapping. * Older qlogicisp driver expects to have the IO space enable * bit set. Things stop working if we program the controllers as not * having PCI_COMMAND_MEMORY, so we have to fudge the mem_flags. */ pci_set_master(d); pci_read_config_word(d, PCI_COMMAND, &command); command |= PCI_COMMAND_MEMORY; command |= PCI_COMMAND_IO; pci_write_config_word(d, PCI_COMMAND, command); d->resource[1].flags |= 1; pci_enable_swapping(d); }
static void __init pci_fixup_isp2x00(struct pci_dev *d) { unsigned int bus_id = (unsigned) d->bus->number; bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], bus_to_wid[bus_id]); bridgereg_t devreg; int i; int slot = PCI_SLOT(d->devfn); unsigned int start; unsigned short command; printk("PCI: Fixing isp2x00 in [bus:slot.fn] %s\n", d->slot_name); /* set the resource struct for this device */ start = (u32) (u64)bridge; /* yes, we want to lose the upper 32 bits here */ start |= BRIDGE_DEVIO(slot); d->resource[0].start = start; d->resource[0].end = d->resource[0].start + 0xff; d->resource[0].flags = IORESOURCE_IO; d->resource[1].start = start; d->resource[1].end = d->resource[0].start + 0xfff; d->resource[1].flags = IORESOURCE_MEM; /* * set the bridge device(x) reg for this device */ devreg = bridge->b_device[slot].reg; /* point device(x) to it appropriate small window */ devreg &= ~BRIDGE_DEV_OFF_MASK; devreg |= (start >> 20) & BRIDGE_DEV_OFF_MASK; bridge->b_device[slot].reg = devreg; pci_enable_swapping(d); /* set card's base addr reg */ //pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x500001); //pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, 0x8b00000); //pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, 0x8b20000); /* I got these from booting irix on system...*/ pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x200001); //pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, 0xf800000); pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, 0x10200000); pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, start); //pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, (start | 0x20000)); /* set cache line size */ pci_conf0_write_config_dword(d, PCI_CACHE_LINE_SIZE, 0xf080); /* set pci bus timeout */ bridge->b_bus_timeout |= BRIDGE_BUS_PCI_RETRY_HLD(0x3); bridge->b_wid_tflush; printk("PCI: bridge bus timeout= 0x%x \n", bridge->b_bus_timeout); /* set host error field */ bridge->b_int_host_err = 0x44; bridge->b_wid_tflush; bridge->b_wid_tflush; /* wait until Bridge PIO complete */ for (i=0; i<8; i++) printk("PCI: device(%d)= 0x%x\n",i,bridge->b_device[i].reg); /* configure device to allow bus mastering, i/o and memory mapping */ pci_set_master(d); pci_read_config_word(d, PCI_COMMAND, &command); command |= PCI_COMMAND_MEMORY; command |= PCI_COMMAND_IO; pci_write_config_word(d, PCI_COMMAND, command); /*d->resource[1].flags |= 1;*/ }