/* Config the VIA chip */ void mpc85xx_config_via(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *tab) { pci_dev_t bridge; unsigned int cmdstat; /* Enable USB and IDE functions */ pci_hose_write_config_byte(hose, dev, 0x48, 0x08); pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER; pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); /* * Force the backplane P2P bridge to have a window * open from 0x00000000-0x00001fff in PCI I/O space. * This allows legacy I/O (i8259, etc) on the VIA * southbridge to be accessed. */ bridge = PCI_BDF(0,BRIDGE_ID,0); pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); }
static void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus) { struct pci_region *pci_mem = hose->pci_mem; struct pci_region *pci_io = hose->pci_io; unsigned int cmdstat; pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); /* Configure bus number registers */ pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev)); pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus); pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); if (pci_mem) { /* Round memory allocator to 1MB boundary */ pciauto_region_align(pci_mem, 0x100000); /* Set up memory and I/O filter limits, assume 32-bit I/O space */ pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE, (pci_mem->bus_lower & 0xfff00000) >> 16); cmdstat |= PCI_COMMAND_MEMORY; } if (pci_io) { /* Round I/O allocator to 4KB boundary */ pciauto_region_align(pci_io, 0x1000); pci_hose_write_config_byte(hose, dev, PCI_IO_BASE, (pci_io->bus_lower & 0x0000f000) >> 8); pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16, (pci_io->bus_lower & 0xffff0000) >> 16); cmdstat |= PCI_COMMAND_IO; } /* We don't support prefetchable memory for now, so disable */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); /* Enable memory and I/O accesses, enable bus master */ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); }
/* * Unlock the configuration bit so that the host system can begin booting * * This should be used after you have: * 1) Called mpc83xx_pci_init() * 2) Set up your inbound translation windows to the appropriate size */ void mpc83xx_pcislave_unlock(int bus) { struct pci_controller *hose = &pci_hose[bus]; u32 dev; u16 reg16; /* Unlock configuration lock in PCI function configuration register */ dev = PCI_BDF(hose->first_busno, 0, 0); pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, ®16); reg16 &= ~(PCI_FUNCTION_CFG_LOCK); pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16); /* The configuration bit is now unlocked, so we can scan the bus */ hose->last_busno = pci_hose_scan(hose); }
void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *entry) { struct pci_pip405_config_entry *table; int i; table = (struct pci_pip405_config_entry*) entry->priv[0]; for (i=0; table[i].width; i++) { #ifdef DEBUG printf("Reg 0x%02X Value 0x%08lX Width %02d written\n", table[i].index, table[i].val, table[i].width); #endif switch(table[i].width) { case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break; case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break; case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break; } } }
void pci_mpc8250_init (struct pci_controller *hose) { u16 tempShort; volatile immap_t *immap = (immap_t *) CFG_IMMR; pci_dev_t host_devno = PCI_BDF (0, 0, 0); pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG, CFG_IMMR + PCI_CFG_DATA_REG); /* * Setting required to enable local bus for PCI (SIUMCR [LBPC]). */ #ifdef CONFIG_MPC8266ADS immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) | SIUMCR_LBPC01; #elif defined CONFIG_MPC8272 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_BBD & ~SIUMCR_ESE & ~SIUMCR_PBSE & ~SIUMCR_CDIS & ~SIUMCR_DPPC11 & ~SIUMCR_L2CPC11 & ~SIUMCR_LBPC11 & ~SIUMCR_APPC11 & ~SIUMCR_CS10PC11 & ~SIUMCR_BCTLC11 & ~SIUMCR_MMR11) | SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 | SIUMCR_APPC10 | SIUMCR_CS10PC00 | SIUMCR_BCTLC00 | SIUMCR_MMR11; #elif defined(CONFIG_TQM8272) /* nothing to do for this Board here */ #else /* * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), * and local bus for PCI (SIUMCR [LBPC]). */ immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11 & ~SIUMCR_CS10PC11 & ~SIUMCR_LBPC11) | SIUMCR_LBPC01 | SIUMCR_CS10PC01 | SIUMCR_APPC10; #endif /* Make PCI lowest priority */ /* Each 4 bits is a device bus request and the MS 4bits is highest priority */ /* Bus 4bit value --- ---------- CPM high 0b0000 CPM middle 0b0001 CPM low 0b0010 PCI reguest 0b0011 Reserved 0b0100 Reserved 0b0101 Internal Core 0b0110 External Master 1 0b0111 External Master 2 0b1000 External Master 3 0b1001 The rest are reserved */ immap->im_siu_conf.sc_ppc_alrh = 0x61207893; /* Park bus on core while modifying PCI Bus accesses */ immap->im_siu_conf.sc_ppc_acr = 0x6; /* * Set up master windows that allow the CPU to access PCI space. These * windows are set up using the two SIU PCIBR registers. */ immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK; immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE; #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK; immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE; #endif /* Release PCI RST (by default the PCI RST signal is held low) */ immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN); /* give it some time */ { #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 /* Give the PCI cards more time to initialize before query This might be good for other boards also */ int i; for (i = 0; i < 1000; ++i) #endif udelay (1000); } /* * Set up master window that allows the CPU to access PCI Memory (prefetch) * space. This window is set up using the first set of Outbound ATU registers. */ immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */ immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */ immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */ /* * Set up master window that allows the CPU to access PCI Memory (non-prefetch) * space. This window is set up using the second set of Outbound ATU registers. */ immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */ immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */ immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */ /* * Set up master window that allows the CPU to access PCI IO space. This window * is set up using the third set of Outbound ATU registers. */ immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */ immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */ immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */ /* * Set up slave window that allows PCI masters to access MPC826x local memory. * This window is set up using the first set of Inbound ATU registers */ immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */ immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */ immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */ /* See above for description - puts PCI request as highest priority */ #ifdef CONFIG_MPC8272 immap->im_siu_conf.sc_ppc_alrh = 0x01236745; #else immap->im_siu_conf.sc_ppc_alrh = 0x03124567; #endif /* Park the bus on the PCI */ immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; /* Host mode - specify the bridge as a host-PCI bridge */ pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE, PCI_CLASS_BRIDGE_CTLR); /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */ pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort); pci_hose_write_config_word (hose, host_devno, PCI_COMMAND, tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* do some bridge init, should be done on all 8260 based bridges */ pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE, 0x08); pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER, 0xF8); hose->first_busno = 0; hose->last_busno = 0xff; /* System memory space */ #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 pci_set_region (hose->regions + 0, PCI_SLV_MEM_BUS, PCI_SLV_MEM_LOCAL, gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); #else pci_set_region (hose->regions + 0, CFG_SDRAM_BASE, CFG_SDRAM_BASE, 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY); #endif /* PCI memory space */ #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 pci_set_region (hose->regions + 1, PCI_MSTR_MEMIO_BUS, PCI_MSTR_MEMIO_LOCAL, PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM); #else pci_set_region (hose->regions + 1, PCI_MSTR_MEM_BUS, PCI_MSTR_MEM_LOCAL, PCI_MSTR_MEM_SIZE, PCI_REGION_MEM); #endif /* PCI I/O space */ pci_set_region (hose->regions + 2, PCI_MSTR_IO_BUS, PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO); hose->region_count = 3; pci_register_hose (hose); /* Mask off master abort machine checks */ immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP); eieio (); hose->last_busno = pci_hose_scan (hose); /* clear the error in the error status register */ immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); /* unmask master abort machine checks */ immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); }
static void pci_init_bus(int bus, struct pci_region *reg) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile pot83xx_t *pot = immr->ios.pot; volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus]; struct pci_controller *hose = &pci_hose[bus]; u32 dev; u16 reg16; int i; if (bus == 1) pot += 3; /* Setup outbound translation windows */ for (i = 0; i < 3; i++, reg++, pot++) { if (reg->size == 0) break; hose->regions[i] = *reg; hose->region_count++; pot->potar = reg->bus_start >> 12; pot->pobar = reg->phys_start >> 12; pot->pocmr = ~(reg->size - 1) >> 12; if (reg->flags & PCI_REGION_IO) pot->pocmr |= POCMR_IO; #ifdef CONFIG_83XX_PCI_STREAMING else if (reg->flags & PCI_REGION_PREFETCH) pot->pocmr |= POCMR_SE; #endif if (bus == 1) pot->pocmr |= POCMR_DST; pot->pocmr |= POCMR_EN; } /* Point inbound translation at RAM */ pci_ctrl->pitar1 = 0; pci_ctrl->pibar1 = 0; pci_ctrl->piebar1 = 0; pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1)); i = hose->region_count++; hose->regions[i].bus_start = 0; hose->regions[i].phys_start = 0; hose->regions[i].size = gd->ram_size; hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; hose->first_busno = pci_last_busno() + 1; hose->last_busno = 0xff; pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80, CONFIG_SYS_IMMR + 0x8304 + bus * 0x80); pci_register_hose(hose); /* * Write to Command register */ reg16 = 0xff; dev = PCI_BDF(hose->first_busno, 0, 0); pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif #ifndef CONFIG_PCISLAVE /* * Hose scan. */ hose->last_busno = pci_hose_scan(hose); #endif }
void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; #ifdef CONFIG_PCI1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; struct pci_config_table *table; struct pci_region *r = hose->regions; uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter" ); /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BASE, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCI1_IO_BASE, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; /* relocate config table pointers */ hose->config_table = \ (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); for (table = hose->config_table; table && table->vendor; table++) table->config_device += gd->reloc_off; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); #ifdef CONFIG_PCIX_CHECK if (!(gur->pordevsr & PORDEVSR_PCI)) { /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) printf("PCI-X will only work at 66 MHz\n"); reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); } #endif } else { printf (" PCI: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ #endif #ifdef CONFIG_PCI2 { uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ if (pci_dual) { printf (" PCI2: 32 bit, 66 MHz, %s\n", pci2_clk_sel ? "sync" : "async"); } else { printf (" PCI2: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ #endif /* CONFIG_PCI2 */ #ifdef CONFIG_PCIE1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); struct pci_region *r = hose->regions; int pcie_configured = io_sel >= 1; if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", pcie_ep ? "End Point" : "Root Complex", (uint)pci); if (pci->pme_msg_det) { pci->pme_msg_det = 0xffffffff; debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); } printf ("\n"); /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); first_free_busno=hose->last_busno+1; } else { printf (" PCIE: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ #endif }
/************************************************************************** * pci_init_board() * * NOTICE: PCI2 is not supported. There is only one * physical PCI slot on the board. * */ void pci_init_board(void) { volatile immap_t * immr; volatile clk83xx_t * clk; volatile law83xx_t * pci_law; volatile pot83xx_t * pci_pot; volatile pcictrl83xx_t * pci_ctrl; volatile pciconf83xx_t * pci_conf; u16 reg16; u32 reg32; u32 dev; struct pci_controller * hose; immr = (immap_t *)CONFIG_SYS_IMMR; clk = (clk83xx_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; pci_ctrl = immr->pci_ctrl; pci_conf = immr->pci_conf; hose = &pci_hose[0]; /* * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode */ reg32 = clk->occr; udelay(2000); clk->occr = 0xff000000; udelay(2000); /* * Release PCI RST Output signal */ pci_ctrl[0].gcr = 0; udelay(2000); pci_ctrl[0].gcr = 1; #ifdef CONFIG_MPC83XX_PCI2 pci_ctrl[1].gcr = 0; udelay(2000); pci_ctrl[1].gcr = 1; #endif /* We need to wait at least a 1sec based on PCI specs */ { int i; for (i = 0; i < 1000; ++i) udelay (1000); } /* * Configure PCI Local Access Windows */ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; /* * Configure PCI Outbound Translation Windows */ /* PCI1 mem space - prefetch */ pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI1 IO space */ pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* PCI1 mmio - non-prefetch mem space */ pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* * Configure PCI Inbound Translation Windows */ /* we need RAM mapped to PCI space for the devices to * access main memory */ pci_ctrl[0].pitar1 = 0x0; pci_ctrl[0].pibar1 = 0x0; pci_ctrl[0].piebar1 = 0x0; pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); hose->first_busno = 0; hose->last_busno = 0xff; /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, CONFIG_SYS_PCI1_MEM_BASE, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM|PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, CONFIG_SYS_PCI1_MMIO_BASE, CONFIG_SYS_PCI1_MMIO_PHYS, CONFIG_SYS_PCI1_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, CONFIG_SYS_PCI1_IO_BASE, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); /* System memory space */ pci_set_region(hose->regions + 3, CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; pci_setup_indirect(hose, (CONFIG_SYS_IMMR+0x8300), (CONFIG_SYS_IMMR+0x8304)); pci_register_hose(hose); /* * Write to Command register */ reg16 = 0xff; dev = PCI_BDF(hose->first_busno, 0, 0); pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif /* * Hose scan. */ hose->last_busno = pci_hose_scan(hose); #ifdef CONFIG_MPC83XX_PCI2 hose = &pci_hose[1]; /* * Configure PCI Outbound Translation Windows */ /* PCI2 mem space - prefetch */ pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI2 IO space */ pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* PCI2 mmio - non-prefetch mem space */ pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); /* * Configure PCI Inbound Translation Windows */ /* we need RAM mapped to PCI space for the devices to * access main memory */ pci_ctrl[1].pitar1 = 0x0; pci_ctrl[1].pibar1 = 0x0; pci_ctrl[1].piebar1 = 0x0; pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); hose->first_busno = pci_hose[0].last_busno + 1; hose->last_busno = 0xff; /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, CONFIG_SYS_PCI2_MEM_BASE, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM|PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, CONFIG_SYS_PCI2_MMIO_BASE, CONFIG_SYS_PCI2_MMIO_PHYS, CONFIG_SYS_PCI2_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, CONFIG_SYS_PCI2_IO_BASE, CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); /* System memory space */ pci_set_region(hose->regions + 3, CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; pci_setup_indirect(hose, (CONFIG_SYS_IMMR+0x8380), (CONFIG_SYS_IMMR+0x8384)); pci_register_hose(hose); /* * Write to Command register */ reg16 = 0xff; dev = PCI_BDF(hose->first_busno, 0, 0); pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); /* * Hose scan. */ hose->last_busno = pci_hose_scan(hose); #endif }
void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info[4]; u32 devdisr, pordevsr, io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; int first_free_busno = 0; int num = 0; int pcie_ep, pcie_configured; devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); porpllsr = in_be32(&gur->porpllsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); #ifdef CONFIG_PCI1 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { SET_STD_PCI_INFO(pci_info[num], 1); pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pci1_hose, first_free_busno); #ifdef CONFIG_PCIX_CHECK if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) { /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) printf("PCI-X will only work at 66 MHz\n"); reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); } #endif } else { printf (" PCI: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif #ifdef CONFIG_PCI2 { uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ if (pci_dual) { printf (" PCI2: 32 bit, 66 MHz, %s\n", pci2_clk_sel ? "sync" : "async"); } else { printf (" PCI2: disabled\n"); } } #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ #endif /* CONFIG_PCI2 */ #ifdef CONFIG_PCIE1 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { printf (" PCIE1: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif }
void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value) { pci_hose_write_config_word(get_hose(), dev, where, value); }
static inline void init_pci1(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_PCI1 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; /* PORDEVSR[15] */ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[14] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORPLLSR[16] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; int pci_agent = fsl_setup_hose(hose, CONFIG_SYS_PCI1_ADDR); uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33333333) ? "33" : (pci_speed == 66666666) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter"); /* outbound memory */ pci_set_region (r++, CONFIG_SYS_PCI1_MEM_BASE, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region (r++, CONFIG_SYS_PCI1_IO_BASE, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); printf (" PCI on bus %02x..%02x\n", hose->first_busno, hose->last_busno); first_free_busno = hose->last_busno + 1; #ifdef CONFIG_PCIX_CHECK if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { ushort reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; uint dev = PCI_BDF(hose->first_busno, 0, 0); /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) puts ("PCI-X will only work at 66 MHz\n"); pci_hose_write_config_word (hose, dev, PCIX_COMMAND, reg16); } #endif } else { puts ("PCI1: disabled\n"); } #else /* !CONFIG_PCI1 */ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ #endif /* CONFIG_PCI1 */ }
void pci_mpc83xx_init(volatile struct pci_controller *hose) { volatile immap_t * immr; volatile clk8349_t * clk; volatile law8349_t * pci_law; volatile pot8349_t * pci_pot; volatile pcictrl8349_t * pci_ctrl; volatile pciconf8349_t * pci_conf; u8 val8,tmp8,ret; u16 reg16,tmp16; u32 val32,tmp32; immr = (immap_t *)CFG_IMMRBAR; clk = (clk8349_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; pci_ctrl = immr->pci_ctrl; pci_conf = immr->pci_conf; /* * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode */ val32 = clk->occr; udelay(2000); clk->occr = 0xff000000; udelay(2000); /* * Configure PCI Local Access Windows */ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; /* * Configure PCI Outbound Translation Windows */ pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); /* mapped to PCI1 IO space 0x0 to local 0xe2000000 */ pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK); /* mapped to PCI2 IO space 0x0 to local 0xe3000000 */ pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); /* * Configure PCI Inbound Translation Windows */ pci_ctrl[0].pitar1 = 0x0; pci_ctrl[0].pibar1 = 0x0; pci_ctrl[0].piebar1 = 0x0; pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; pci_ctrl[1].pitar1 = 0x0; pci_ctrl[1].pibar1 = 0x0; pci_ctrl[1].piebar1 = 0x0; pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; /* * Assign PIB PMC slot to desired PCI bus */ #ifdef CONFIG_MPC8349ADS mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET); i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE); #endif val8 = 0; ret = i2c_write(0x23,0x6,1,&val8,1); ret = i2c_write(0x23,0x7,1,&val8,1); val8 = 0xff; ret = i2c_write(0x23,0x2,1,&val8,1); ret = i2c_write(0x23,0x3,1,&val8,1); val8 = 0; ret = i2c_write(0x26,0x6,1,&val8,1); val8 = 0x34; ret = i2c_write(0x26,0x7,1,&val8,1); #if defined(PCI_64BIT) val8 = 0xf4; /* PMC2<->PCI1 64bit */ #elif defined(PCI_ALL_PCI1) val8 = 0xf3; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit */ #elif defined(PCI_ONE_PCI1) val8 = 0xf9; /* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit */ #elif defined(PCI_TWO_PCI1) val8 = 0xf5; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */ #else val8 = 0xf5; #endif ret = i2c_write(0x26,0x2,1,&val8,1); val8 = 0xff; ret = i2c_write(0x26,0x3,1,&val8,1); val8 = 0; ret = i2c_write(0x27,0x6,1,&val8,1); ret = i2c_write(0x27,0x7,1,&val8,1); val8 = 0xff; ret = i2c_write(0x27,0x2,1,&val8,1); val8 = 0xef; ret = i2c_write(0x27,0x3,1,&val8,1); asm("eieio"); /* * Release PCI RST Output signal */ udelay(2000); pci_ctrl[0].gcr = 1; #ifndef PCI_64BIT pci_ctrl[1].gcr = 1; #endif udelay(2000); hose[0].first_busno = 0; hose[0].last_busno = 0xff; pci_set_region(hose[0].regions + 0, CFG_PCI1_MEM_BASE, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); pci_set_region(hose[0].regions + 1, CFG_PCI1_IO_BASE, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); hose[0].region_count = 2; pci_setup_indirect(&hose[0], (CFG_IMMRBAR+0x8300), (CFG_IMMRBAR+0x8304)); #define PCI_CLASS_BRIDGE 0x06 reg16 = 0xff; tmp32 = 0xffff; pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE); pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_STATUS, 0xffff); pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); #ifndef PCI_64BIT hose[1].first_busno = 0; hose[1].last_busno = 0xff; pci_set_region(hose[1].regions + 0, CFG_PCI2_MEM_BASE, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_SIZE, PCI_REGION_MEM); pci_set_region(hose[1].regions + 1, CFG_PCI2_IO_BASE, CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO); hose[1].region_count = 2; pci_setup_indirect(&hose[1], (CFG_IMMRBAR+0x8380), (CFG_IMMRBAR+0x8384)); pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE); pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_STATUS, 0xffff); pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); #endif #if defined(PCI_64BIT) printf("PCI1 64bit on PMC2\n"); #elif defined(PCI_ALL_PCI1) printf("PCI1 32bit on PMC1 & PMC2 & PMC3\n"); #elif defined(PCI_ONE_PCI1) printf("PCI1 32bit on PMC1,PCI2 32bit on PMC2 & PMC3\n"); #else printf("PCI1 32bit on PMC1 & PMC2 & PMC3 in default\n"); #endif #if 1 /* * Hose scan. */ pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); #endif }
void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info; u32 devdisr, pordevsr, io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; int first_free_busno = 0; char buf[32]; devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); porpllsr = in_be32(&gur->porpllsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); #ifdef CONFIG_PCI1 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { SET_STD_PCI_INFO(pci_info, 1); set_next_law(pci_info.mem_phys, law_size_bits(pci_info.mem_size), pci_info.law); set_next_law(pci_info.io_phys, law_size_bits(pci_info.io_size), pci_info.law); pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, strmhz(buf, pci_speed), pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", pci_info.regs); pci1_hose.config_table = pci_mpc85xxcds_config_table; first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); #ifdef CONFIG_PCIX_CHECK if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) { /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) printf("PCI-X will only work at 66 MHz\n"); reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); } #endif } else { printf("PCI1: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif #ifdef CONFIG_PCI2 { uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ if (pci_dual) { printf("PCI2: 32 bit, 66 MHz, %s\n", pci2_clk_sel ? "sync" : "async"); } else { printf("PCI2: disabled\n"); } } #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ #endif /* CONFIG_PCI2 */ fsl_pcie_init_board(first_free_busno); }
/************************************************************************** * pci_init_board() * */ void pci_init_board(void) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile law512x_t *pci_law; volatile pot512x_t *pci_pot; volatile pcictrl512x_t *pci_ctrl; volatile pciconf512x_t *pci_conf; u16 reg16; u32 reg32; u32 dev; int i; struct pci_controller *hose; /* Set PCI divider for 33MHz */ reg32 = in_be32(&im->clk.scfr[0]); reg32 &= ~(SCFR1_PCI_DIV_MASK); reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT; out_be32(&im->clk.scfr[0], reg32); clrsetbits_be32(&im->clk.scfr[0], SCFR1_PCI_DIV_MASK, SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT ); pci_law = im->sysconf.pcilaw; pci_pot = im->ios.pot; pci_ctrl = &im->pci_ctrl; pci_conf = &im->pci_conf; hose = &pci_hose; /* * Release PCI RST Output signal */ out_be32(&pci_ctrl->gcr, 0); udelay(2000); out_be32(&pci_ctrl->gcr, 1); /* We need to wait at least a 1sec based on PCI specs */ for (i = 0; i < 1000; i++) udelay(1000); /* * Configure PCI Local Access Windows */ out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR); out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M); out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR); out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M); /* * Configure PCI Outbound Translation Windows */ /* PCI mem space - prefetch */ out_be32(&pci_pot[0].potar, (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK); out_be32(&pci_pot[0].pobar, (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK); out_be32(&pci_pot[0].pocmr, POCMR_EN | POCMR_PRE | POCMR_CM_256M); /* PCI IO space */ out_be32(&pci_pot[1].potar, (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK); out_be32(&pci_pot[1].pobar, (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK); out_be32(&pci_pot[1].pocmr, POCMR_EN | POCMR_IO | POCMR_CM_16M); /* PCI mmio - non-prefetch mem space */ out_be32(&pci_pot[2].potar, (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK); out_be32(&pci_pot[2].pobar, (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK); out_be32(&pci_pot[2].pocmr, POCMR_EN | POCMR_CM_256M); /* * Configure PCI Inbound Translation Windows */ /* we need RAM mapped to PCI space for the devices to * access main memory */ out_be32(&pci_ctrl[0].pitar1, 0x0); out_be32(&pci_ctrl[0].pibar1, 0x0); out_be32(&pci_ctrl[0].piebar1, 0x0); out_be32(&pci_ctrl[0].piwar1, PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1)); hose->first_busno = 0; hose->last_busno = 0xff; /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BASE, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM|PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_MMIO_BASE, CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_IO_BASE, CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); /* System memory space */ pci_set_region(hose->regions + 3, CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; pci_setup_indirect(hose, (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); pci_register_hose(hose); /* * Write to Command register */ reg16 = 0xff; dev = PCI_BDF(hose->first_busno, 0, 0); pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif /* * Hose scan. */ hose->last_busno = pci_hose_scan(hose); }
/********************************************************************** * pci_init_board() *********************************************************************/ void pci_init_board(void) #ifdef CONFIG_PCISLAVE { u16 reg16; volatile immap_t *immr; volatile law83xx_t *pci_law; volatile pot83xx_t *pci_pot; volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; immr = (immap_t *) CFG_IMMR; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; pci_ctrl = immr->pci_ctrl; pci_conf = immr->pci_conf; /* * Configure PCI Inbound Translation Windows */ pci_ctrl[0].pitar0 = 0x0; pci_ctrl[0].pibar0 = 0x0; pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_4K; pci_ctrl[0].pitar1 = 0x0; pci_ctrl[0].pibar1 = 0x0; pci_ctrl[0].piebar1 = 0x0; pci_ctrl[0].piwar1 &= ~PIWAR_EN; pci_ctrl[0].pitar2 = 0x0; pci_ctrl[0].pibar2 = 0x0; pci_ctrl[0].piebar2 = 0x0; pci_ctrl[0].piwar2 &= ~PIWAR_EN; hose[0].first_busno = 0; hose[0].last_busno = 0xff; pci_setup_indirect(&hose[0], (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); reg16 = 0xff; pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff); pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80); /* * Unlock configuration lock in PCI function configuration register. */ pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), PCI_FUNCTION_CONFIG, ®16); reg16 &= ~(PCI_FUNCTION_CFG_LOCK); pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), PCI_FUNCTION_CONFIG, reg16); printf("Enabled PCI 32bit Agent Mode\n"); }
/************************************************************************** * pci_init_board() * * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since * per TQM834x design physical connections to external devices (PCI sockets) * are routed only to the PCI1 we do not account for the second one - this code * supports PCI1 module only. Should support for the PCI2 be required in the * future it needs a separate pci_controller structure (above) and handling - * please refer to other boards' implementation for dual PCI host controllers, * for example board/Marvell/db64360/pci.c, pci_init_board() * */ void pci_init_board(void) { volatile immap_t * immr; volatile clk83xx_t * clk; volatile law83xx_t * pci_law; volatile pot83xx_t * pci_pot; volatile pcictrl83xx_t * pci_ctrl; volatile pciconf83xx_t * pci_conf; u16 reg16; u32 reg32; struct pci_controller * hose; immr = (immap_t *)CONFIG_SYS_IMMR; clk = (clk83xx_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; pci_ctrl = immr->pci_ctrl; pci_conf = immr->pci_conf; hose = &pci1_hose; /* * Configure PCI controller and PCI_CLK_OUTPUT */ /* * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one * line actually used for clocking all external PCI devices in TQM83xx. * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 * are known to hang the board; this issue is under investigation * (13 oct 05) */ reg32 = OCCR_PCICOE1; #if 0 /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ reg32 = 0xff000000; #endif if (clk->spmr & SPMR_CKID) { /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR * fields accordingly */ reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ | OCCR_PCICD6 | OCCR_PCICD7); } clk->occr = reg32; udelay(2000); /* * Release PCI RST Output signal */ pci_ctrl[0].gcr = 0; udelay(2000); pci_ctrl[0].gcr = 1; udelay(2000); /* * Configure PCI Local Access Windows */ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; /* * Configure PCI Outbound Translation Windows */ /* PCI1 mem space */ pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); /* PCI1 IO space */ pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); /* * Configure PCI Inbound Translation Windows */ /* we need RAM mapped to PCI space for the devices to * access main memory */ pci_ctrl[0].pitar1 = 0x0; pci_ctrl[0].pibar1 = 0x0; pci_ctrl[0].piebar1 = 0x0; pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M; hose->first_busno = 0; hose->last_busno = 0xff; /* PCI memory space */ pci_set_region(hose->regions + 0, CONFIG_SYS_PCI1_MEM_BASE, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 1, CONFIG_SYS_PCI1_IO_BASE, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); /* System memory space */ pci_set_region(hose->regions + 2, CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, CONFIG_PCI_SYS_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); hose->region_count = 3; pci_setup_indirect(hose, (CONFIG_SYS_IMMR+0x8300), (CONFIG_SYS_IMMR+0x8304)); pci_register_hose(hose); /* * Write to Command register */ reg16 = 0xff; pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, 0xffff); pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, 0x80); #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif /* * Hose scan. */ hose->last_busno = pci_hose_scan(hose); }