void bootblock_mainboard_init(void)
{
uint8_t recovery_enabled;
unsigned char addr;
unsigned char byte;
bootblock_northbridge_init();
bootblock_southbridge_init();
/* Recovery jumper is connected to SP5100 GPIO61, and clears the GPIO when placed in the Recovery position */
byte = pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x56);
byte |= 0x1 << 4; /* Set GPIO61 to input mode */
pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);
recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));
if (recovery_enabled) {
#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
/* Clear NVRAM checksum */
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
cmos_write(0x0, addr);
}
/* Set fallback boot */
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0xfc;
cmos_write(byte, RTC_BOOT_BYTE);
#else
/* FIXME
* Figure out how to recover if the option table is not available
*/
#endif
}
}
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
*
* Hardware should enable LPC ROM by pin straps. This function does not
* handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
*
* The HUDSON power-on default is to map 512K ROM space.
*
*/
static void hudson_enable_rom(void)
{
u8 reg8;
pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 3);
/* Decode variable LPC ROM address ranges 1 and 2. */
reg8 = pci_io_read_config8(dev, 0x48);
reg8 |= (1 << 3) | (1 << 4);
pci_io_write_config8(dev, 0x48, reg8);
/* LPC ROM address range 1: */
/* Enable LPC ROM range mirroring start at 0x000e(0000). */
pci_io_write_config16(dev, 0x68, 0x000e);
/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
pci_io_write_config16(dev, 0x6a, 0x000f);
/* LPC ROM address range 2: */
/*
* Enable LPC ROM range start at:
* 0xfff8(0000): 512KB
* 0xfff0(0000): 1MB
* 0xffe0(0000): 2MB
* 0xffc0(0000): 4MB
*/
pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
/* Enable LPC ROM range end at 0xffff(ffff). */
pci_io_write_config16(dev, 0x6e, 0xffff);
}
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
*
* Hardware should enable LPC ROM by pin straps. This function does not
* handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
*
* The SB600 power-on default is to map 256K ROM space.
*
* Details: AMD SB600 BIOS Developer's Guide (BDG), page 15.
*/
static void sb600_enable_rom(void)
{
u8 reg8;
pci_devfn_t dev;
dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
PCI_DEVICE_ID_ATI_SB600_LPC), 0);
/* Decode variable LPC ROM address ranges 1 and 2. */
reg8 = pci_io_read_config8(dev, 0x48);
reg8 |= (1 << 3) | (1 << 4);
pci_io_write_config8(dev, 0x48, reg8);
/* LPC ROM address range 1: */
/* Enable LPC ROM range mirroring start at 0x000e(0000). */
pci_io_write_config16(dev, 0x68, 0x000e);
/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
pci_io_write_config16(dev, 0x6a, 0x000f);
/* LPC ROM address range 2: */
/*
* Enable LPC ROM range start at:
* 0xfff8(0000): 512KB
* 0xfff0(0000): 1MB
* 0xffe0(0000): 2MB
* 0xffc0(0000): 4MB
*/
pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* 4 MB */
/* Enable LPC ROM range end at 0xffff(ffff). */
pci_io_write_config16(dev, 0x6e, 0xffff);
}
static void bootblock_northbridge_init(void)
{
u8 reg;
pci_io_read_config8(PCI_DEV(0, 0x11, 0), 0x41);
reg |= ROM_DECODE_MAP;
pci_io_write_config8(PCI_DEV(0, 0x11, 0), 0x41, reg);
}
static void amd8111_enable_rom(void)
{
unsigned char byte;
device_t dev;
/* Enable 5MB rom access at 0xFFB00000 - 0xFFFFFFFF */
/* Locate the amd8111 */
dev = pci_io_locate_device(PCI_ID(0x1022, 0x7468), 0);
/* Set the 5MB enable bits */
byte = pci_io_read_config8(dev, 0x43);
byte |= 0xC0;
pci_io_write_config8(dev, 0x43, byte);
}
/**
* \brief Enable accessing of PCI configuration space for all devices.
*
* Enable accessing of D0F1 through D0F7, which would otherwise not be
* accessible. If MMCONF is enabled, configure it here. This is the first
* function that should be called in romstage.
*/
void vx900_enable_pci_config_space(void)
{
/* MMCONF is not yet enabled, so we'll need to specify we want to do
* pci_io. We don't want to do pci_mmio until we enable it */
/* Enable multifunction bit for northbridge.
* This enables the PCI configuration spaces of D0F1 to D0F7 to be
* accessed */
pci_io_write_config8(HOST_CTR, 0x4f, 0x01);
/* COOL, now enable MMCONF */
u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60);
reg8 |= 3;
pci_io_write_config8(TRAF_CTR, 0x60, reg8);
reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28;
pci_io_write_config8(TRAF_CTR, 0x61, reg8);
}
