static void enable_mainboard_devices(void)
{
device_t dev;
/* dev 0 for southbridge */
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
pci_write_config8(dev, 0x50, 7);
pci_write_config8(dev, 0x51, 0xff);
#if 0
// This early setup switches IDE into compatibility mode before PCI gets
// a chance to assign I/Os
// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
// movb $0x09, %dl
// movb $0x00, %dl
// PCI_WRITE_CONFIG_BYTE
//
#endif
/* we do this here as in V2, we can not yet do raw operations
* to pci!
*/
/* changed this to work correctly on later revisions of LB.
* The original dev += 0x100; stopped working. It also appears
* that if this is not set here, but in ide_init() only, the IDE
* does not work at all. I assume it needs to be set before something else,
* possibly before enabling the IDE peripheral, or it is a timing issue.
* Ben Hewson 29 Apr 2007.
*/
dev = pci_locate_device(PCI_ID(0x1106,0x0571), 0);
pci_write_config8(dev, 0x42, 0);
}
static void enable_smbus(void)
{
device_t dev;
unsigned char c;
/* Power management controller */
dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
}
// set IO base address to SMBUS_IO_BASE
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
// Enable SMBus
c = pci_read_config8(dev, 0xd2);
c |= 5;
pci_write_config8(dev, 0xd2, c);
/* make it work for I/O ...
*/
dev = pci_locate_device(PCI_ID(0x1106, 0x8231), 0);
c = pci_read_config8(dev, 4);
c |= 1;
pci_write_config8(dev, 4, c);
print_debug_hex8(c);
print_debug(" is the comm register\n");
print_debug("SMBus controller enabled\n");
}
static void bcm5785_enable_wdt_port_cf9(void)
{
pci_devfn_t dev;
uint32_t dword;
uint32_t dword_old;
dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
dword_old = pci_read_config32(dev, 0x4c);
dword = dword_old | (1<<4); //enable Timer Func
if (dword != dword_old ) {
pci_write_config32(dev, 0x4c, dword);
}
dword_old = pci_read_config32(dev, 0x6c);
dword = dword_old | (1<<9); //unhide Timer Func in pci space
if (dword != dword_old ) {
pci_write_config32(dev, 0x6c, dword);
}
dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
/* enable cf9 */
pci_write_config8(dev, 0x40, (1<<2));
}
static void enable_mainboard_devices(void)
{
device_t dev;
dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0);
if (dev == PCI_DEV_INVALID) {
die("LPC bridge not found!!!\n");
}
// Disable GP3
pci_write_config8(dev, 0x98, 0x00);
// Disable mc97
pci_write_config8(dev, 0x50, 0x80);
// Disable internal KBC Configuration
pci_write_config8(dev, 0x51, 0x2d);
pci_write_config8(dev, 0x58, 0x42);
pci_write_config8(dev, 0x59, 0x80);
pci_write_config8(dev, 0x5b, 0x01);
// Enable P2P Bridge Header for External PCI BUS.
dev = pci_locate_device(PCI_ID(0x1106, 0x324e), 0);
if (dev == PCI_DEV_INVALID) {
die("P2P bridge not found!!!\n");
}
pci_write_config8(dev, 0x4f, 0x41);
// Switch SATA to non-RAID mode
dev = pci_locate_device(PCI_ID(0x1106, 0x0581), 0);
if (dev != PCI_DEV_INVALID) {
pci_write_config16(dev, 0xBA, 0x5324);
}
}
static void enable_mainboard_devices(void)
{
device_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
/* bit=0 means enable function (per CX700 datasheet)
* 5 16.1 USB 2
* 4 16.0 USB 1
* 3 15.0 SATA and PATA
* 2 16.2 USB 3
* 1 16.4 USB EHCI
*/
pci_write_config8(dev, 0x50, 0x80);
/* bit=1 means enable internal function (per CX700 datasheet)
* 3 Internal RTC
* 2 Internal PS2 Mouse
* 1 Internal KBC Configuration
* 0 Internal Keyboard Controller
*/
pci_write_config8(dev, 0x51, 0x1d);
}
static void mcp55_enable_rom(void)
{
u8 byte;
u16 word;
device_t addr;
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
#if 0
/* Default MCP55 LPC single */
addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0);
#else
// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0);
addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0);
#endif
/* Set the 15MB enable bits. */
byte = pci_read_config8(addr, 0x88);
byte |= 0xff; /* 256K */
pci_write_config8(addr, 0x88, byte);
byte = pci_read_config8(addr, 0x8c);
byte |= 0xff; /* 1M */
pci_write_config8(addr, 0x8c, byte);
word = pci_read_config16(addr, 0x90);
word |= 0x7fff; /* 15M */
pci_write_config16(addr, 0x90, word);
}
static void bcm5785_enable_msg(void)
{
pci_devfn_t dev;
uint32_t dword;
uint32_t dword_old;
uint8_t byte;
dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
byte = pci_read_config8(dev, 0x42);
byte = (1<<1); //enable a20
pci_write_config8(dev, 0x42, byte);
dword_old = pci_read_config32(dev, 0x6c);
// bit 5: enable A20 Message
// bit 4: enable interrupt messages
// bit 3: enable reset init message
// bit 2: enable keyboard init message
// bit 1: enable upsteam messages
// bit 0: enable shutdowm message to init generation
dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
if (dword != dword_old ) {
pci_write_config32(dev, 0x6c, dword);
}
}
void enable_smbus(void)
{
pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0);
if (dev == PCI_DEV_INVALID) {
/* This won't display text if enable_smbus() is before serial init */
die("Power Managment Controller not found\n");
}
/* Set clock source */
pci_write_config8(dev, 0x94, 0x20);
/* Write SMBus IO base to 0xd0, and enable SMBus */
pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
/* Set to Award value */
pci_write_config8(dev, 0xd2, 0x05);
/* Make it work for I/O ... */
pci_write_config16(dev, 0x04, 0x0003);
smbus_reset();
/* clear host data port */
outb(0x00, SMBHSTDAT0);
SMBUS_DELAY();
smbus_wait_until_ready();
}
static void disable_esb6300_watchdog(void)
{
/* FIXME move me somewhere more appropriate */
device_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID) {
die("Missing 6300ESB?");
}
/* Enable I/O space */
value = pci_read_config16(dev, 0x04);
value |= (1 << 10);
pci_write_config16(dev, 0x04, value);
/* Set and enable acpibase */
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
pci_write_config8(dev, 0x44, 0x10);
base = ICH5_WDBASE + 0x60;
/* Set bit 11 in TCO1_CNT */
value = inw(base + 0x08);
value |= 1 << 11;
outw(value, base + 0x08);
/* Clear TCO timeout status */
outw(0x0008, base + 0x04);
outw(0x0002, base + 0x06);
}
/* RPR 2.28: Get SB ASIC Revision. */
static u8 set_sb700_revision(void)
{
pci_devfn_t dev;
u8 rev_id, enable_14Mhz, byte;
u8 rev = 0;
/* if (rev != 0) return rev; */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
/* NOT REACHED */
}
rev_id = pci_read_config8(dev, 0x08);
if (rev_id == 0x39) {
enable_14Mhz = (pmio_read(0x53) >> 6) & 1;
if (enable_14Mhz == 0x0)
rev = 0x11; /* A11 */
else if (enable_14Mhz == 0x1) {
/* This happens, if does, only once. So later if we need to get
* the revision ID, we don't have to make such a big function.
* We just get reg 0x8 in smbus dev. 0x39 is A11, 0x3A is A12. */
rev = 0x12;
byte = pci_read_config8(dev, 0x40);
byte |= 1 << 0;
pci_write_config8(dev, 0x40, byte);
pci_write_config8(dev, 0x08, 0x3A); /* Change 0x39 to 0x3A. */
byte &= ~(1 << 0);
pci_write_config8(dev, 0x40, byte);
}
} else if (rev_id == 0x3A) { /* A12 will be 0x3A after BIOS is initialized */
static void enable_mainboard_devices(void)
{
device_t dev;
u8 reg;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
/* bit=0 means enable function (per VT8237R datasheet)
* 7 17.6 MC97
* 6 17.5 AC97
* 5 16.1 USB 2
* 4 16.0 USB 1
* 3 15.0 SATA and PATA
* 2 16.2 USB 3
* 1 16.4 USB EHCI
*/
pci_write_config8(dev, 0x50, 0xC0);
/*bit=0 means enable internal function (per VT8237R datasheet)
* 7 USB Device Mode
*bit=1 means enable internal function (per VT8237R datasheet)
* 6 Reserved
* 5 LAN Controller Clock Gating
* 4 LAN Controller
* 3 Internal RTC
* 2 Internal PS2 Mouse
* 1 Internal KBC Configuration
* 0 Internal Keyboard Controller
*/
pci_write_config8(dev, 0x51, 0x9d);
}
void sb600_lpc_port80(void)
{
u8 byte;
device_t dev;
u32 reg32;
/* Enable LPC controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
reg32 = pci_read_config32(dev, 0x64);
reg32 |= 0x00100000; /* lpcEnable */
pci_write_config32(dev, 0x64, reg32);
/* Enable port 80 LPC decode in pci function 3 configuration space. */
dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0);
byte = pci_read_config8(dev, 0x4a);
byte |= 1 << 5; /* enable port 80 */
pci_write_config8(dev, 0x4a, byte);
}
void sb600_pci_port80(void)
{
u8 byte;
device_t dev;
/* P2P Bridge */
dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
/* Chip Control: Enable subtractive decoding */
byte = pci_read_config8(dev, 0x40);
byte |= 1 << 5;
pci_write_config8(dev, 0x40, byte);
/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
byte = pci_read_config8(dev, 0x4B);
byte |= 1 << 7;
pci_write_config8(dev, 0x4B, byte);
/* The same IO Base and IO Limit here is meaningful because we set the
* bridge to be subtractive. During early setup stage, we have to make
* sure that data can go through port 0x80.
*/
/* IO Base: 0xf000 */
byte = pci_read_config8(dev, 0x1C);
byte |= 0xF << 4;
pci_write_config8(dev, 0x1C, byte);
/* IO Limit: 0xf000 */
byte = pci_read_config8(dev, 0x1D);
byte |= 0xF << 4;
pci_write_config8(dev, 0x1D, byte);
/* PCI Command: Enable IO response */
byte = pci_read_config8(dev, 0x04);
byte |= 1 << 0;
pci_write_config8(dev, 0x04, byte);
/* LPC controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
byte = pci_read_config8(dev, 0x4A);
byte &= ~(1 << 5); /* disable lpc port 80 */
pci_write_config8(dev, 0x4A, byte);
}
/* RPR 2.1: Get SB ASIC Revision. */
static u8 get_sb600_revision(void)
{
device_t dev;
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
/* NOT REACHED */
}
return pci_read_config8(dev, 0x08);
}
static void sis966_enable_rom(void)
{
pci_devfn_t addr;
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
addr = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS,
PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
/* Set the 4MB enable bit(s). */
pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11);
}
/***************************************
* Legacy devices are mapped to LPC space.
* Serial port 0, 1
* KBC Port
* ACPI Micro-controller port
* This function does not change port 0x80 decoding.
* Console output through any port besides 0x2f8/0x3f8 is unsupported.
* If you use FWH ROMs, you have to setup IDSEL.
* Reviewed-by: Carl-Daniel Hailfinger
* Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1
* (LPC ISA Bridge)
***************************************/
static void sb600_lpc_init(void)
{
u8 reg8;
u32 reg32;
device_t dev;
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */
/* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
* This bit has no meaning if debug strap is not enabled. So if the
* board keeps rebooting and the code fails to reach here, we could
* disable the debug strap first. */
reg32 = pci_read_config32(dev, 0x4C);
reg32 |= 1 << 31;
pci_write_config32(dev, 0x4C, reg32);
/* Enable lpc controller */
reg32 = pci_read_config32(dev, 0x64);
reg32 |= 1 << 20;
pci_write_config32(dev, 0x64, reg32);
dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); /* LPC Controller */
/* Decode port 0x3f8-0x3ff (Serial 0), 0x2f8-0x2ff (Serial 1) */
reg8 = pci_read_config8(dev, 0x44);
reg8 |= (1 << 6) | (1 << 7);
pci_write_config8(dev, 0x44, reg8);
/* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/
reg8 = pci_read_config8(dev, 0x47);
reg8 |= (1 << 5) | (1 << 6);
pci_write_config8(dev, 0x47, reg8);
/* Super I/O, RTC */
reg8 = pci_read_config8(dev, 0x48);
/* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */
reg8 |= (1 << 1) | (1 << 0);
/* Decode port 0x70-0x73 (RTC) */
reg8 |= (1 << 6);
pci_write_config8(dev, 0x48, reg8);
}
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
static void bcm5785_enable_rom(void)
{
u8 byte;
device_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS,
PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0);
/* Set the 4MB enable bits. */
byte = pci_read_config8(dev, 0x41);
byte |= 0x0e;
pci_write_config8(dev, 0x41, byte);
}
static void enable_smbus(void)
{
device_t dev;
unsigned char c;
int i;
/* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8235), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
}
// set IO base address to SMBUS_IO_BASE
pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
// Enable SMBus
pci_write_config8(dev, 0xd2, (0x4 << 1) | 1);
/* make it work for I/O ...
*/
pci_write_config16(dev, 4, 1);
/* FIX for half baud rate problem */
/* let clocks and the like settle */
/* as yet arbitrary count - 1000 is too little 5000 works */
for(i = 0 ; i < 5000 ; i++)
outb(0x80,0x80);
/*
* The VT1211 serial port needs 48 mhz clock, on power up it is getting
* only 24 mhz, there is some mysterious device on the smbus that can
* fix this...this code below does it.
* */
outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0);
outb(0x83, SMBUS_IO_BASE+SMBHSTCMD);
outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD);
outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL);
for (;;) {
c = inb(SMBUS_IO_BASE+SMBHSTSTAT);
if ((c & 1) == 0)
break;
}
}
static void enable_smbus(void)
{
pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
}
printk(BIOS_DEBUG, "SMBus controller enabled\n");
/* set smbus iobase */
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
/* Set smbus iospace enable */
pci_write_config8(dev, 0xd2, 0x03);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
}
static void enable_smbus(void)
{
device_t dev;
dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0);
if (dev == PCI_DEV_INVALID)
die("SMBus controller not found\n");
print_debug("SMBus controller enabled\n");
/* Set SMBus I/O base. */
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
/* Set SMBus I/O space enable. */
pci_write_config16(dev, 0x4, 0x01);
/* Clear any lingering errors, so the transaction will run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
}
static void bcm5785_enable_lpc(void)
{
uint8_t byte;
pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
/* LPC Control 0 */
byte = pci_read_config8(dev, 0x44);
/* Serial 0 */
byte |= (1<<6);
pci_write_config8(dev, 0x44, byte);
/* LPC Control 4 */
byte = pci_read_config8(dev, 0x48);
/* superio port 0x2e/4e enable */
byte |=(1<<1)|(1<<0);
pci_write_config8(dev, 0x48, byte);
}
static void enable_vt8231_serial(void)
{
uint8_t c;
device_t dev;
outb(6, 0x80);
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
if (dev == PCI_DEV_INVALID) {
outb(7, 0x80);
die("Serial controller not found\n");
}
/* first, you have to enable the superio and superio config.
put a 6 reg 80
*/
c = pci_read_config8(dev, 0x50);
c |= 6;
pci_write_config8(dev, 0x50, c);
outb(2, 0x80);
// now go ahead and set up com1.
// set address
vt8231_writesuper(0xf4, 0xfe);
// enable serial out
vt8231_writesuper(0xf2, 7);
// That's it for the sio stuff.
// movl $SUPERIOCONFIG, %eax
// movb $9, %dl
// PCI_WRITE_CONFIG_BYTE
// set up reg to set baud rate.
vt8231_writesiobyte(0x3fb, 0x80);
// Set 115 kb
vt8231_writesioword(0x3f8, 1);
// Set 9.6 kb
// WRITESIOWORD(0x3f8, 12)
// now set no parity, one stop, 8 bits
vt8231_writesiobyte(0x3fb, 3);
// now turn on RTS, DRT
vt8231_writesiobyte(0x3fc, 3);
// Enable interrupts
vt8231_writesiobyte(0x3f9, 0xf);
// should be done. Dump a char for fun.
vt8231_writesiobyte(0x3f8, 48);
}
/**
* Enable the serial port(s) of the VT82C686(A/B) Super I/O chip.
*
* @param dev TODO
* @param iobase TODO
*/
static void vt82c686_enable_serial(device_t dev, unsigned iobase)
{
uint8_t reg;
device_t sbdev;
/* TODO: Use info from 'dev' and 'iobase'. */
/* TODO: Only enable one serial port (depending on config) or both? */
/* (1) Enter configuration mode (set Function 0 Rx85[1] = 1). */
/* Find the southbridge. Die upon error. */
sbdev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_82C686), 0);
// sbdev = PCI_DEV(0, 7, 0);
if (sbdev == PCI_DEV_INVALID) {
/* Serial output is not yet working at this point, but
* die() emits the POST code 0xff and halts the CPU, too. */
die("Southbridge not found.\n");
}
/* Enable Super-I/O (bit 0) and Super-I/O Configuration (bit 1). */
reg = pci_read_config8(sbdev, 0x85);
pci_write_config8(sbdev, 0x85, reg | 0x3); /* Set bits 0 and 1. */
/* (2) Configure the chip. */
/* Enable serial port 1 (set bit 2) and 2 (set bit 3). */
vt82c686_sio_write(VT82C686_FS, 0xf);
// vt82c686_sio_write(VT82C686_POWER, 0x00); /* No powerdown */
// vt82c686_sio_write(VT82C686_SP_CTRL, 0x00); /* Normal operation */
vt82c686_sio_write(VT82C686_SP1, 0xfe); /* SP1: 0x3f8 */
vt82c686_sio_write(VT82C686_SP2, 0xbe); /* SP2: 0x2f8 */
/* Enable high speed on serial port 1 (set bit 6) and 2 (set bit 7). */
vt82c686_sio_write(VT82C686_SP_CFG, 0xc0);
/* (3) Exit configuration mode (set Function 0 Rx85[1] = 0). */
reg = pci_read_config8(sbdev, 0x85);
pci_write_config8(sbdev, 0x85, reg & 0xfd); /* Clear bit 1. */
}
static void disable_jarell_frb3(void)
{
#if 0
device_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID) {
die("Missing esb6300?");
}
/* Enable I/O space */
value = pci_read_config16(dev, 0x04);
value |= (1 << 0);
pci_write_config16(dev, 0x04, value);
/* Set gpio base */
pci_write_config32(dev, 0x58, ESB6300_GPIOBASE | 1);
base = ESB6300_GPIOBASE;
/* Enable GPIO Bar */
value = pci_read_config32(dev, 0x5c);
value |= 0x10;
pci_write_config32(dev, 0x5c, value);
/* Configure GPIO 48 and 40 as GPIO */
value = inl(base + 0x30);
value |= (1 << 16) | ( 1 << 8);
outl(value, base + 0x30);
/* Configure GPIO 48 as Output */
value = inl(base + 0x34);
value &= ~(1 << 16);
outl(value, base + 0x34);
/* Toggle GPIO 48 high to low */
value = inl(base + 0x38);
value |= (1 << 16);
outl(value, base + 0x38);
value &= ~(1 << 16);
outl(value, base + 0x38);
#endif
}
static void bootblock_southbridge_init(void)
{
u16 reg16;
pci_devfn_t dev;
/*
* Note: The Intel 82371AB/EB/MB ISA device can be on different
* PCI bus:device.function locations on different boards.
* Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
* But scanning for the PCI IDs (instead of hardcoding
* bus/device/function numbers) works on all boards.
*/
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82371AB_ISA), 0);
/* Enable access to the whole ROM, disable ROM write access. */
reg16 = pci_read_config16(dev, XBCS);
reg16 |= LOWER_BIOS_ENABLE | EXT_BIOS_ENABLE | EXT_BIOS_ENABLE_1MB;
reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */
pci_write_config16(dev, XBCS, reg16);
}
static void vt8231_enable_rom(void)
{
device_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8231), 0);
/*
* ROM decode control register (0x43):
*
* Bit Decode range
* -----------------
* 7 0xFFFE0000-0xFFFEFFFF
* 6 0xFFF80000-0xFFFDFFFF
* 5 0xFFF00000-0xFFF7FFFF
* 4 0x000E0000-0x000EFFFF
* 3 0x000D8000-0x000DFFFF
* 2 0x000D0000-0x000D7FFF
* 1 0x000C8000-0x000CFFFF
* 0 0x000C0000-0x000C7FFF
*/
pci_write_config8(dev, 0x43, (1 << 7) | (1 << 6) | (1 << 5));
}
void enable_pm(void)
{
device_t dev;
u8 reg8;
u16 reg16;
/* Get the SMBus/PM device of the 82371AB/EB/MB. */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
/* Set the PM I/O base. */
pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1);
/* Enable access to the PM I/O space. */
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 |= PCI_COMMAND_IO;
pci_write_config16(dev, PCI_COMMAND, reg16);
/* PM I/O Space Enable (PMIOSE). */
reg8 = pci_read_config8(dev, PMREGMISC);
reg8 |= PMIOSE;
pci_write_config8(dev, PMREGMISC, reg8);
}
static void enable_smbus(void)
{
device_t dev;
uint8_t enable;
dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
}
pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
enable = pci_read_config8(dev, 0x41);
pci_write_config8(dev, 0x41, enable | (1 << 7));
/* check that we can see the smbus controller I/O. */
if (inw(SMBUS_IO_BASE)==0xFF){
die("SMBUS controller I/O not found\n");
}
/* clear any lingering errors, so the transaction will run */
outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
print_spew("SMBus controller enabled\n");
}
/* sbDevicesPorInitTable */
static void sb600_devices_por_init(void)
{
device_t dev;
u8 byte;
printk(BIOS_INFO, "sb600_devices_por_init()\n");
/* SMBus Device, BDF:0-20-0 */
printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
/* NOT REACHED */
}
printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n",
get_sb600_revision());
/* sbPorAtStartOfTblCfg */
/* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
* This is an I/O address. The I/O address must be on 16-byte boundary. */
pci_write_config32(dev, 0xf0, AB_INDX);
/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
/*Enables the SB600 to send transactions upstream over A-Link Express interface. */
axcfg_reg(0x04, 1 << 2, 1 << 2);
axindxc_reg(0x21, 0xff, 0);
/* 2.3.5:Enabling Non-Posted Memory Write for the K8 Platform */
axindxc_reg(0x10, 1 << 9, 1 << 9);
/* END of sbPorAtStartOfTblCfg */
/* sbDevicesPorInitTables */
/* set smbus iobase */
pci_write_config32(dev, 0x10, SMBUS_IO_BASE | 1);
/* enable smbus controller interface */
byte = pci_read_config8(dev, 0xd2);
byte |= (1 << 0);
pci_write_config8(dev, 0xd2, byte);
/* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */
pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11);
/* TODO: I don't know the usage of followed two lines. I copied them from CIM. */
pci_write_config8(dev, 0x0a, 0x1);
pci_write_config8(dev, 0x0b, 0x6);
/* KB2RstEnable */
pci_write_config8(dev, 0x40, 0xd4);
/* Enable ISA Address 0-960K decoding */
pci_write_config8(dev, 0x48, 0x0f);
/* Enable ISA Address 0xC0000-0xDFFFF decode */
pci_write_config8(dev, 0x49, 0xff);
/* Enable decode cycles to IO C50, C51, C52 GPM controls. */
byte = pci_read_config8(dev, 0x41);
byte &= 0x80;
byte |= 0x33;
pci_write_config8(dev, 0x41, byte);
/* Legacy DMA Prefetch Enhancement, CIM masked it. */
/* pci_write_config8(dev, 0x43, 0x1); */
/* Disabling Legacy USB Fast SMI# */
byte = pci_read_config8(dev, 0x62);
byte |= 0x24;
pci_write_config8(dev, 0x62, byte);
/* Features Enable */
pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */
/* SerialIrq Control */
pci_write_config8(dev, 0x69, 0x90);
/* Test Mode, PCIB_SReset_En Mask is set. */
pci_write_config8(dev, 0x6c, 0x20);
/* IO Address Enable, CIM set 0x78 only and masked 0x79. */
/*pci_write_config8(dev, 0x79, 0x4F); */
pci_write_config8(dev, 0x78, 0xFF);
/* This register is not used on sb600. It came from older chipset. */
/*pci_write_config8(dev, 0x95, 0xFF); */
/* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */
pci_write_config16(dev, 0x4, 0x0407);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* IDE Device, BDF:0-20-1 */
printk(BIOS_INFO, "sb600_devices_por_init(): IDE Device, BDF:0-20-1\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
/* Disable prefetch */
byte = pci_read_config8(dev, 0x63);
byte |= 0x1;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
printk(BIOS_INFO, "sb600_devices_por_init(): LPC Device, BDF:0-20-3\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
/* DMA enable */
pci_write_config8(dev, 0x40, 0x04);
/* LPC Sync Timeout */
pci_write_config8(dev, 0x49, 0xFF);
/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
pci_write_config8(dev, 0x7C, 0x05);
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
* TODO: I don't know what are their mean? */
printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
/* I don't know why CIM tried to write into a read-only reg! */
/*pci_write_config8(dev, 0x0c, 0x20) */ ;
/* Arbiter enable. */
pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into height priority list. */
/* pci_write_config8(dev, 0x49, 0x1) */ ;
pci_write_config8(dev, 0x40, 0x26);
/* I don't know why CIM set reg0x1c as 0x11.
* System will block at sdram_initialize() if I set it before call sdram_initialize().
* If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize().
* pci_write_config8(dev, 0x1c, 0x11);
* pci_write_config8(dev, 0x1d, 0x11);*/
/*CIM set this register; but I didn't find its description in RPR.
On DBM690T platform, I didn't find different between set and skip this register.
But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed
after the bit0 of this register is set.
pci_write_config8(dev, 0x04, 0x21);
*/
pci_write_config8(dev, 0x0d, 0x40);
pci_write_config8(dev, 0x1b, 0x40);
/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
pci_write_config8(dev, 0x50, 0x01);
/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
printk(BIOS_INFO, "sb600_devices_por_init(): SATA Device, BDF:0-18-0\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
/*PHY Global Control, we are using A14.
* default: 0x2c40 for ASIC revision A12 and below
* 0x2c00 for ASIC revision A13 and above.*/
pci_write_config16(dev, 0x86, 0x2C00);
/* PHY Port0-3 Control */
pci_write_config32(dev, 0x88, 0xB400DA);
pci_write_config32(dev, 0x8c, 0xB400DA);
pci_write_config32(dev, 0x90, 0xB400DA);
pci_write_config32(dev, 0x94, 0xB400DA);
/* Port0-3 BIST Control/Status */
pci_write_config8(dev, 0xa5, 0xB8);
pci_write_config8(dev, 0xad, 0xB8);
pci_write_config8(dev, 0xb5, 0xB8);
pci_write_config8(dev, 0xbd, 0xB8);
}
/*
* Compliant with CIM_48's sbPciCfg.
* Add any south bridge setting.
*/
static void sb600_pci_cfg(void)
{
device_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
/* Enable the hidden revision ID, available after A13. */
byte = pci_read_config8(dev, 0x70);
byte |= (1 << 8);
pci_write_config8(dev, 0x70, byte);
/* rpr2.20 Disable Timer IRQ Enhancement for proper operation of the 8254 timer, 0xae[5]. */
byte = pci_read_config8(dev, 0xae);
byte |= (1 << 5);
pci_write_config8(dev, 0xae, byte);
/* Enable watchdog decode timer */
byte = pci_read_config8(dev, 0x41);
byte |= (1 << 3);
pci_write_config8(dev, 0x41, byte);
/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
* generated PCIRST#. */
byte = pmio_read(0x65);
byte |= (1 << 4);
pmio_write(0x65, byte);
/*For A13 and above. */
if (get_sb600_revision() > 0x12) {
/* rpr2.16 C-State Reset, PMIO 0x9f[7]. */
byte = pmio_read(0x9f);
byte |= (1 << 7);
pmio_write(0x9f, byte);
/* rpr2.17 PCI Clock Period will increase to 30.8ns. 0x53[7]. */
byte = pmio_read(0x53);
byte |= (1 << 7);
pmio_write(0x53, byte);
}
/* IDE Device, BDF:0-20-1 */
dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
/* Enable IDE Explicit prefetch, 0x63[0] clear */
byte = pci_read_config8(dev, 0x63);
byte &= 0xfe;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
/* rpr7.2 Enabling LPC DMA function. */
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);
pci_write_config8(dev, 0x40, byte);
/* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */
byte = pci_read_config8(dev, 0x48);
byte &= 0x7f;
pci_write_config8(dev, 0x48, byte);
/* rpr7.5 Disabling LPC MSI Capability, 0x78[1] clear. */
byte = pci_read_config8(dev, 0x78);
byte &= 0xfd;
pci_write_config8(dev, 0x78, byte);
/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
/* rpr6.8 Disabling SATA MSI Capability, for A13 and above, 0x42[7]. */
if (0x12 < get_sb600_revision()) {
u32 reg32;
reg32 = pci_read_config32(dev, 0x40);
reg32 |= (1 << 23);
pci_write_config32(dev, 0x40, reg32);
}
/* EHCI Device, BDF:0-19-5, ehci usb controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4386), 0);
/* rpr5.10 Disabling USB EHCI MSI Capability. 0x50[6]. */
byte = pci_read_config8(dev, 0x50);
byte |= (1 << 6);
pci_write_config8(dev, 0x50, byte);
/* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */
dev = pci_locate_device(PCI_ID(0x1002, 0x4387), 0);
/* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */
byte = pci_read_config8(dev, 0x41);
byte |= 0x1f;
pci_write_config8(dev, 0x41, byte);
}
