static int pch_gbe_recv(struct eth_device *dev)
{
struct pch_gbe_priv *priv = dev->priv;
struct pch_gbe_regs *mac_regs = priv->mac_regs;
struct pch_gbe_rx_desc *rx_head, *rx_desc;
u32 hw_desc, buffer_addr, length;
int rx_swp;
rx_head = &priv->rx_desc[0];
rx_desc = &priv->rx_desc[priv->rx_idx];
readl(&mac_regs->int_st);
hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
/* Just return if not receiving any packet */
if ((u32)rx_desc == hw_desc)
return 0;
buffer_addr = pci_mem_to_phys(priv->bdf, rx_desc->buffer_addr);
length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
NetReceive((uchar *)buffer_addr, length);
/* Test the wrap-around condition */
if (++priv->rx_idx >= PCH_GBE_DESC_NUM)
priv->rx_idx = 0;
rx_swp = priv->rx_idx;
if (++rx_swp >= PCH_GBE_DESC_NUM)
rx_swp = 0;
writel(pci_phys_to_mem(priv->bdf, (u32)(rx_head + rx_swp)),
&mac_regs->rx_dsc_sw_p);
return length;
}
unsigned int pci_video_init(void)
{
GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
pci_dev_t devbusfn;
if ((devbusfn = pci_find_devices(supported, 0)) < 0)
{
printf ("PCI video controller not found!\n");
return 0;
}
/* PCI setup */
pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pGD->frameAdrs);
pGD->frameAdrs = pci_mem_to_phys (devbusfn, pGD->frameAdrs);
if (pGD->frameAdrs == 0) {
printf ("PCI config: failed to get base address\n");
return 0;
}
pGD->pciBase = pGD->frameAdrs;
/* Setup clocks and memory mode for Coral-P Eval. Board */
HOST_WR_REG (0x0038, 0x00090000);
udelay (200);
HOST_WR_REG (0xfffc, 0x11d7fa13);
udelay (100);
return pGD->frameAdrs;
}
static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *_)
{
unsigned int iobase;
unsigned short status = 0;
unsigned char timer;
/*
* Configure PLX PCI9054
*/
pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
/* Check the latency timer for values >= 0x60.
*/
pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
if (timer < 0x60)
{
pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
}
/* Set I/O base register.
*/
pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
if (pci9054_iobase == 0xffffffff)
{
printf("Error: Can not set I/O base register.\n");
return;
}
}
int pch_gbe_register(bd_t *bis)
{
struct eth_device *dev;
struct pch_gbe_priv *priv;
pci_dev_t devno;
u32 iobase;
devno = pci_find_devices(supported, 0);
if (devno == -1)
return -ENODEV;
dev = (struct eth_device *)malloc(sizeof(*dev));
if (!dev)
return -ENOMEM;
memset(dev, 0, sizeof(*dev));
/*
* The priv structure contains the descriptors and frame buffers which
* need a strict buswidth alignment (64 bytes)
*/
priv = (struct pch_gbe_priv *)memalign(PCH_GBE_ALIGN_SIZE,
sizeof(*priv));
if (!priv) {
free(dev);
return -ENOMEM;
}
memset(priv, 0, sizeof(*priv));
dev->priv = priv;
priv->dev = dev;
priv->bdf = devno;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
iobase = pci_mem_to_phys(devno, iobase);
dev->iobase = iobase;
priv->mac_regs = (struct pch_gbe_regs *)iobase;
sprintf(dev->name, "pch_gbe.%x", iobase);
/* Read MAC address from SROM and initialize dev->enetaddr with it */
pch_gbe_mac_read(priv->mac_regs, dev->enetaddr);
dev->init = pch_gbe_init;
dev->halt = pch_gbe_halt;
dev->send = pch_gbe_send;
dev->recv = pch_gbe_recv;
eth_register(dev);
priv->interface = PHY_INTERFACE_MODE_RGMII;
pch_gbe_mdio_init(dev->name, priv->mac_regs);
priv->bus = miiphy_get_dev_by_name(dev->name);
return pch_gbe_phy_init(dev);
}
int rtl8169_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase;
int idx=0;
while(1){
unsigned int region;
u16 device;
/* Find RTL8169 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_word(devno, PCI_DEVICE_ID, &device);
switch (device) {
case 0x8168:
region = 2;
break;
default:
region = 1;
break;
}
pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
iobase &= ~0xf;
debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
if (!dev) {
printf("Can not allocate memory of rtl8169\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "RTL8169#%d", card_number);
dev->priv = (void *) devno;
dev->iobase = (int)pci_mem_to_phys(devno, iobase);
dev->init = rtl_reset;
dev->halt = rtl_halt;
dev->send = rtl_send;
dev->recv = rtl_recv;
eth_register (dev);
rtl_init(dev, bis);
card_number++;
}
return card_number;
}
/* Find the base address to talk tot he HDA codec.
*/
static u32 get_hda_base(void)
{
pci_dev_t devbusfn;
u32 pci_mem_base;
devbusfn = pci_find_devices(supported, 0);
if (devbusfn < 0) {
printf("Audio: Controller not found !\n");
return 0;
}
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
pci_mem_base = pci_mem_to_phys(devbusfn, pci_mem_base);
return pci_mem_base;
}
unsigned int pci_video_init (void)
{
GraphicDevice *dev = &mb862xx;
pci_dev_t devbusfn;
u16 device;
if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
puts("controller not present\n");
return 0;
}
/* PCI setup */
pci_write_config_dword (devbusfn, PCI_COMMAND,
(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
if (dev->frameAdrs == 0) {
puts ("PCI config: failed to get base address\n");
return 0;
}
dev->pciBase = dev->frameAdrs;
puts("Coral-");
pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
switch (device) {
case PCI_DEVICE_ID_CORAL_P:
puts("P\n");
break;
case PCI_DEVICE_ID_CORAL_PA:
puts("PA\n");
break;
default:
puts("Unknown\n");
return 0;
}
/* Setup clocks and memory mode for Coral-P(A) */
HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
udelay (200);
HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
udelay (100);
return dev->frameAdrs;
}
static void rtl8169_init_ring(pci_dev_t dev)
#endif
{
int i;
#ifdef DEBUG_RTL8169
int stime = currticks();
printf ("%s\n", __FUNCTION__);
#endif
tpc->cur_rx = 0;
tpc->cur_tx = 0;
tpc->dirty_tx = 0;
memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
for (i = 0; i < NUM_TX_DESC; i++) {
tpc->Tx_skbuff[i] = &txb[i];
}
for (i = 0; i < NUM_RX_DESC; i++) {
if (i == (NUM_RX_DESC - 1))
tpc->RxDescArray[i].status =
cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
else
tpc->RxDescArray[i].status =
cpu_to_le32(OWNbit + RX_BUF_SIZE);
tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
#ifdef CONFIG_DM_ETH
tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
#else
tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
#endif
rtl_flush_rx_desc(&tpc->RxDescArray[i]);
}
#ifdef DEBUG_RTL8169
printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
#endif
}
int rtl8169_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase;
int idx=0;
while(1){
/* Find RTL8169 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0xf;
debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
sprintf (dev->name, "RTL8169#%d", card_number);
dev->priv = (void *) devno;
dev->iobase = (int)pci_mem_to_phys(devno, iobase);
dev->init = rtl_reset;
dev->halt = rtl_halt;
dev->send = rtl_send;
dev->recv = rtl_recv;
eth_register (dev);
rtl_init(dev, bis);
card_number++;
}
return card_number;
}
static void rtl8169_hw_start(pci_dev_t dev)
#endif
{
u32 i;
#ifdef DEBUG_RTL8169
int stime = currticks();
printf ("%s\n", __FUNCTION__);
#endif
#if 0
/* Soft reset the chip. */
RTL_W8(ChipCmd, CmdReset);
/* Check that the chip has finished the reset. */
for (i = 1000; i > 0; i--) {
if ((RTL_R8(ChipCmd) & CmdReset) == 0)
break;
else
udelay(10);
}
#endif
RTL_W8(Cfg9346, Cfg9346_Unlock);
/* RTL-8169sb/8110sb or previous version */
if (tpc->chipset <= 5)
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
RTL_W8(EarlyTxThres, EarlyTxThld);
/* For gigabit rtl8169 */
RTL_W16(RxMaxSize, RxPacketMaxSize);
/* Set Rx Config register */
i = rtl8169_rx_config | (RTL_R32(RxConfig) &
rtl_chip_info[tpc->chipset].RxConfigMask);
RTL_W32(RxConfig, i);
/* Set DMA burst size and Interframe Gap Time */
RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
(InterFrameGap << TxInterFrameGapShift));
tpc->cur_rx = 0;
#ifdef CONFIG_DM_ETH
RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)tpc->TxDescArray));
#else
RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)tpc->TxDescArray));
#endif
RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
#ifdef CONFIG_DM_ETH
RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
#else
RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
#endif
RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
/* RTL-8169sc/8110sc or later version */
if (tpc->chipset > 5)
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
RTL_W8(Cfg9346, Cfg9346_Lock);
udelay(10);
RTL_W32(RxMissed, 0);
rtl8169_set_rx_mode();
/* no early-rx interrupts */
RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
#ifdef DEBUG_RTL8169
printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
#endif
}
static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
void *packet, int length)
#endif
{
/* send the packet to destination */
u32 to;
u8 *ptxb;
int entry = tpc->cur_tx % NUM_TX_DESC;
u32 len = length;
int ret;
#ifdef DEBUG_RTL8169_TX
int stime = currticks();
printf ("%s\n", __FUNCTION__);
printf("sending %d bytes\n", len);
#endif
ioaddr = dev_iobase;
/* point to the current txb incase multiple tx_rings are used */
ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
memcpy(ptxb, (char *)packet, (int)length);
while (len < ETH_ZLEN)
ptxb[len++] = '\0';
rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
tpc->TxDescArray[entry].buf_Haddr = 0;
#ifdef CONFIG_DM_ETH
tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
#else
tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
#endif
if (entry != (NUM_TX_DESC - 1)) {
tpc->TxDescArray[entry].status =
cpu_to_le32((OWNbit | FSbit | LSbit) |
((len > ETH_ZLEN) ? len : ETH_ZLEN));
} else {
tpc->TxDescArray[entry].status =
cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
((len > ETH_ZLEN) ? len : ETH_ZLEN));
}
rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
RTL_W8(TxPoll, 0x40); /* set polling bit */
tpc->cur_tx++;
to = currticks() + TX_TIMEOUT;
do {
rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
} while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
&& (currticks() < to)); /* wait */
if (currticks() >= to) {
#ifdef DEBUG_RTL8169_TX
puts("tx timeout/error\n");
printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
#endif
ret = -ETIMEDOUT;
} else {
#ifdef DEBUG_RTL8169_TX
puts("tx done\n");
#endif
ret = 0;
}
/* Delay to make net console (nc) work properly */
udelay(20);
return ret;
}
static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
uchar **packetp)
#endif
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
/* nic->packetlen should contain length of data */
int cur_rx;
int length = 0;
#ifdef DEBUG_RTL8169_RX
printf ("%s\n", __FUNCTION__);
#endif
ioaddr = dev_iobase;
cur_rx = tpc->cur_rx;
rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
status) & 0x00001FFF) - 4;
rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
if (cur_rx == NUM_RX_DESC - 1)
tpc->RxDescArray[cur_rx].status =
cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
else
tpc->RxDescArray[cur_rx].status =
cpu_to_le32(OWNbit + RX_BUF_SIZE);
#ifdef CONFIG_DM_ETH
tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
dm_pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)
tpc->RxBufferRing[cur_rx]));
#else
tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
tpc->RxBufferRing[cur_rx]));
#endif
rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
#ifdef CONFIG_DM_ETH
*packetp = rxdata;
#else
net_process_received_packet(rxdata, length);
#endif
} else {
puts("Error Rx");
length = -EIO;
}
cur_rx = (cur_rx + 1) % NUM_RX_DESC;
tpc->cur_rx = cur_rx;
return length;
} else {
ushort sts = RTL_R8(IntrStatus);
RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
udelay(100); /* wait */
}
tpc->cur_rx = cur_rx;
return (0); /* initially as this is called to flush the input */
}
/*-----------------------------------------------------------------------------
* video_hw_init --
*-----------------------------------------------------------------------------
*/
void *video_hw_init (void)
{
#ifdef CONFIG_VIDEO_SM501_PCI
unsigned int pci_mem_base, pci_mmio_base;
unsigned int id;
unsigned short device_id;
pci_dev_t devbusfn;
int mem;
#endif
unsigned int *vm, i;
memset (&sm501, 0, sizeof (GraphicDevice));
#ifdef CONFIG_VIDEO_SM501_PCI
printf("Video: ");
/* Look for SM501/SM502 chips */
devbusfn = pci_find_devices(sm501_pci_tbl, 0);
if (devbusfn < 0) {
printf ("PCI Controller not found.\n");
goto not_pci;
}
/* Setup */
pci_write_config_dword (devbusfn, PCI_COMMAND,
(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
pci_read_config_dword (devbusfn, PCI_REVISION_ID, &id);
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_1, &pci_mmio_base);
sm501.frameAdrs = pci_mem_to_phys (devbusfn, pci_mem_base);
sm501.isaBase = pci_mem_to_phys (devbusfn, pci_mmio_base);
if (sm501.isaBase)
write_reg32 = write_le32;
mem = in_le32 ((unsigned __iomem *)(sm501.isaBase + 0x10));
mem = (mem & 0x0000e000) >> 13;
switch (mem) {
case 1:
mem = 8;
break;
case 2:
mem = 16;
break;
case 3:
mem = 32;
break;
case 4:
mem = 64;
break;
case 5:
mem = 2;
break;
case 0:
default:
mem = 4;
}
printf ("PCI SM50%d %d MB\n", ((id & 0xff) == 0xC0) ? 2 : 1, mem);
not_pci:
#endif
/*
* Initialization of the access to the graphic chipset Retreive base
* address of the chipset (see board/RPXClassic/eccx.c)
*/
if (!sm501.isaBase) {
sm501.isaBase = board_video_init ();
if (!sm501.isaBase)
return NULL;
}
if (!sm501.frameAdrs) {
sm501.frameAdrs = board_video_get_fb ();
if (!sm501.frameAdrs)
return NULL;
}
sm501.winSizeX = board_get_width ();
sm501.winSizeY = board_get_height ();
#if defined(CONFIG_VIDEO_SM501_8BPP)
sm501.gdfIndex = GDF__8BIT_INDEX;
sm501.gdfBytesPP = 1;
#elif defined(CONFIG_VIDEO_SM501_16BPP)
sm501.gdfIndex = GDF_16BIT_565RGB;
sm501.gdfBytesPP = 2;
#elif defined(CONFIG_VIDEO_SM501_32BPP)
sm501.gdfIndex = GDF_32BIT_X888RGB;
sm501.gdfBytesPP = 4;
#else
#error Unsupported SM501 BPP
#endif
sm501.memSize = sm501.winSizeX * sm501.winSizeY * sm501.gdfBytesPP;
/* Load Smi registers */
SmiSetRegs ();
/* (see board/RPXClassic/RPXClassic.c) */
board_validate_screen (sm501.isaBase);
/* Clear video memory */
i = sm501.memSize/4;
vm = (unsigned int *)sm501.frameAdrs;
while(i--)
*vm++ = 0;
return (&sm501);
}
