void intel_sandybridge_finalize_smm(void) { pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ pci_or_config16(PCI_DEV_SNB, 0x58, 1 << 2); /* PAVP Lock */ pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ MCHBAR32_OR(0x6800, 1 << 31); MCHBAR32_OR(0x7000, 1 << 31); MCHBAR32_OR(0x77fc, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(0x50fc) = 0x8f; /* Read+write the following */ MCHBAR32(0x6030) = MCHBAR32(0x6030); MCHBAR32(0x6034) = MCHBAR32(0x6034); MCHBAR32(0x6008) = MCHBAR32(0x6008); }
/* Handler for XHCI controller on entry to S3/S4/S5 */ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) { u16 reg16; u32 reg32; u8 *mem_base = usb_xhci_mem_base(dev); if (!mem_base || slp_typ < ACPI_S3) return; if (pch_is_lp()) { /* Set D0 state */ reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); reg16 &= ~PWR_CTL_SET_MASK; reg16 |= PWR_CTL_SET_D0; pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); /* Clear PCI 0xB0[14:13] */ reg32 = pci_read_config32(dev, 0xb0); reg32 &= ~((1 << 14) | (1 << 13)); pci_write_config32(dev, 0xb0, reg32); /* Clear MMIO 0x816c[14,2] */ reg32 = read32(mem_base + 0x816c); reg32 &= ~((1 << 14) | (1 << 2)); write32(mem_base + 0x816c, reg32); /* Reset disconnected USB3 ports */ usb_xhci_reset_usb3(dev, 0); /* Set MMIO 0x80e0[15] */ reg32 = read32(mem_base + 0x80e0); reg32 |= (1 << 15); write32(mem_base + 0x80e0, reg32); } /* Set D3Hot state and enable PME */ pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_SET_D3); pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_STATUS_PME); pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME); }
void intel_pch_finalize_smm(void) { if (CONFIG_LOCK_SPI_ON_RESUME_RO || CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) { /* Copy flash regions from FREG0-4 to PR0-4 and enable write protection bit31 */ int i; u32 lockmask = (1 << 31); if (CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) lockmask |= (1 << 15); for (i = 0; i < 20; i += 4) RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; } /* Set SPI opcode menu */ RCBA16(0x3894) = SPI_OPPREFIX; RCBA16(0x3896) = SPI_OPTYPE; RCBA32(0x3898) = SPI_OPMENU_LOWER; RCBA32(0x389c) = SPI_OPMENU_UPPER; /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); #if CONFIG_SPI_FLASH_SMM /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif /* TCLOCKDN: TC Lockdown */ RCBA32_OR(0x0050, (1 << 31)); /* BIOS Interface Lockdown */ RCBA32_OR(0x3410, (1 << 0)); /* Function Disable SUS Well Lockdown */ RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); pci_write_config32(PCI_DEV(0, 27, 0), 0x74, pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); }
void intel_pch_finalize_smm(void) { /* Set SPI opcode menu */ RCBA16(0x3894) = SPI_OPPREFIX; RCBA16(0x3896) = SPI_OPTYPE; RCBA32(0x3898) = SPI_OPMENU_LOWER; RCBA32(0x389c) = SPI_OPMENU_UPPER; /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); #if CONFIG_SPI_FLASH_SMM /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif /* TCLOCKDN: TC Lockdown */ RCBA32_OR(0x0050, (1 << 31)); /* BIOS Interface Lockdown */ RCBA32_OR(0x3410, (1 << 0)); /* Function Disable SUS Well Lockdown */ RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); pci_write_config32(PCI_DEV(0, 27, 0), 0x74, pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); }