void intel_sandybridge_finalize_smm(void)
{
pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */
pci_or_config16(PCI_DEV_SNB, 0x58, 1 << 2); /* PAVP Lock */
pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */
pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */
pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */
pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */
pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */
pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */
pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */
pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */
pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */
pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */
MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */
MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */
MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */
MCHBAR32_OR(0x6800, 1 << 31);
MCHBAR32_OR(0x7000, 1 << 31);
MCHBAR32_OR(0x77fc, 1 << 0);
/* Memory Controller Lockdown */
MCHBAR8(0x50fc) = 0x8f;
/* Read+write the following */
MCHBAR32(0x6030) = MCHBAR32(0x6030);
MCHBAR32(0x6034) = MCHBAR32(0x6034);
MCHBAR32(0x6008) = MCHBAR32(0x6008);
}
static void pch_pcie_init(struct device *dev)
{
u16 reg16;
printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
/* Enable SERR */
pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
/* Enable Bus Master */
pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Set Cache Line Size to 0x10 */
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE);
/* disable parity error response, enable ISA */
pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2);
if (IS_ENABLED(CONFIG_PCIE_DEBUG_INFO)) {
printk(BIOS_SPEW, " MBL = 0x%08x\n",
pci_read_config32(dev, PCI_MEMORY_BASE));
printk(BIOS_SPEW, " PMBL = 0x%08x\n",
pci_read_config32(dev, PCI_PREF_MEMORY_BASE));
printk(BIOS_SPEW, " PMBU32 = 0x%08x\n",
pci_read_config32(dev, PCI_PREF_BASE_UPPER32));
printk(BIOS_SPEW, " PMLU32 = 0x%08x\n",
pci_read_config32(dev, PCI_PREF_LIMIT_UPPER32));
}
/* Clear errors in status registers */
reg16 = pci_read_config16(dev, PCI_STATUS);
pci_write_config16(dev, PCI_STATUS, reg16);
reg16 = pci_read_config16(dev, PCI_SEC_STATUS);
pci_write_config16(dev, PCI_SEC_STATUS, reg16);
}
void usb_ehci_disable(device_t dev)
{
u16 reg16;
u32 reg32;
/* Set 0xDC[0]=1 */
pci_or_config32(dev, 0xdc, (1 << 0));
/* Set D3Hot state and disable PME */
reg16 = pci_read_config16(dev, EHCI_PWR_CTL_STS);
reg16 &= ~(PWR_CTL_ENABLE_PME | PWR_CTL_SET_MASK);
reg16 |= PWR_CTL_SET_D3;
pci_write_config16(dev, EHCI_PWR_CTL_STS, reg16);
/* Clear memory and bus master */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Disable device */
switch (dev) {
case PCH_EHCI1_DEV:
RCBA32_OR(FD, PCH_DISABLE_EHCI1);
break;
case PCH_EHCI2_DEV:
RCBA32_OR(FD, PCH_DISABLE_EHCI2);
break;
}
}
static void hide_hsuarts(void)
{
int i;
printk(BIOS_DEBUG, "HIDING HSUARTs.\n");
/* There is a hardware requirement to hide functions starting from the
last one. */
for (i = DENVERTON_UARTS_TO_INI - 1; i >= 0; i--) {
struct device *uart_dev;
uart_dev = dev_find_slot(0, PCI_DEVFN(HSUART_DEV, i));
if (uart_dev == NULL)
continue;
pci_or_config32(uart_dev, PCI_FUNC_RDCFG_HIDE, 1);
}
}
