u_int32_t
eeprom_get_byte (long addr)
{
u_int32_t input;
u_int32_t data;
int count;
/* Start the Reading of DATA
**
** The first read is a dummy as the data is latched in the
** EPLD and read on the next read access to the EEPROM.
*/
input = pci_read_32 ((u_int32_t *) addr);
data = 0;
count = NUM_OF_BITS;
while (--count >= 0)
{
eeprom_delay ();
input = pci_read_32 ((u_int32_t *) addr);
data <<= 1; /* Shift data over */
data |= (input & EPROM_ACTIVE_IN_BIT) ? 1 : 0;
}
return data;
}
u_int32_t
eeprom_get_byte (long addr)
{
u_int32_t input;
u_int32_t data;
int count;
/*
*/
input = pci_read_32 ((u_int32_t *) addr);
data = 0;
count = NUM_OF_BITS;
while (--count >= 0)
{
eeprom_delay ();
input = pci_read_32 ((u_int32_t *) addr);
data <<= 1; /* */
data |= (input & EPROM_ACTIVE_IN_BIT) ? 1 : 0;
}
return data;
}
int
pmc_eeprom_write (long addr, long mem_offset, u_int32_t data)
{
volatile u_int32_t temp;
int count;
if (!ByteReverseBuilt)
BuildByteReverse ();
mem_offset = ByteReverse[0x7F & mem_offset];
mem_offset <<= 2;
mem_offset |= EPROM_WRITE;
eeprom_put_byte (addr, mem_offset, SIZE_ADDR_OP);
data = ByteReverse[0xFF & data];
eeprom_put_byte (addr, data, NUM_OF_BITS);
pci_write_32 ((u_int32_t *) addr, 0);
pci_write_32 ((u_int32_t *) addr, EPROM_ENCS);
temp = pci_read_32 ((u_int32_t *) addr);
temp = pci_read_32 ((u_int32_t *) addr);
if (temp & EPROM_ACTIVE_IN_BIT)
{
temp = pci_read_32 ((u_int32_t *) addr);
if (temp & EPROM_ACTIVE_IN_BIT)
{
pci_write_32 ((u_int32_t *) addr, 0);
return (1);
}
}
count = 1000;
while (count--)
{
for (temp = 0; temp < 0x10; temp++)
OS_uwait_dummy ();
if (pci_read_32 ((u_int32_t *) addr) & EPROM_ACTIVE_IN_BIT)
break;
}
if (count == -1)
return (2);
return (0);
}
int
pmc_eeprom_write (long addr, long mem_offset, u_int32_t data)
{
volatile u_int32_t temp;
int count;
if (!ByteReverseBuilt)
BuildByteReverse ();
mem_offset = ByteReverse[0x7F & mem_offset]; /* Reverse address */
/*
* NOTE: The max offset address is 128 or half the reversal table. So the
* LSB is always zero and counts as a built in shift of one bit. So even
* though we need to shift 3 bits to make room for the command, we only
* need to shift twice more because of the built in shift.
*/
mem_offset <<= 2; /* Shift for command */
mem_offset |= EPROM_WRITE; /* Add command */
eeprom_put_byte (addr, mem_offset, SIZE_ADDR_OP); /* Output chip address */
data = ByteReverse[0xFF & data];/* Reverse data */
eeprom_put_byte (addr, data, NUM_OF_BITS); /* Output chip data */
pci_write_32 ((u_int32_t *) addr, 0); /* Remove Chip Select from
* EEPROM */
/*
** Must see Data In at a low state before completing this transaction.
**
** Afterwards, the data bit will return to a high state, ~6 ms, terminating
** the operation.
*/
pci_write_32 ((u_int32_t *) addr, EPROM_ENCS); /* Re-enable Chip Select */
temp = pci_read_32 ((u_int32_t *) addr); /* discard first read */
temp = pci_read_32 ((u_int32_t *) addr);
if (temp & EPROM_ACTIVE_IN_BIT)
{
temp = pci_read_32 ((u_int32_t *) addr);
if (temp & EPROM_ACTIVE_IN_BIT)
{
pci_write_32 ((u_int32_t *) addr, 0); /* Remove Chip Select
* from EEPROM */
return (1);
}
}
count = 1000;
while (count--)
{
for (temp = 0; temp < 0x10; temp++)
OS_uwait_dummy ();
if (pci_read_32 ((u_int32_t *) addr) & EPROM_ACTIVE_IN_BIT)
break;
}
if (count == -1)
return (2);
return (0);
}
void
VMETRO_TRIGGER (ci_t * ci, int x)
{
comet_t *comet;
volatile u_int32_t data;
comet = ci->port[0].cometbase; /* default to COMET # 0 */
switch (x)
{
default:
case 0:
data = pci_read_32 ((u_int32_t *) &comet->__res24); /* 0x90 */
break;
case 1:
data = pci_read_32 ((u_int32_t *) &comet->__res25); /* 0x94 */
break;
case 2:
data = pci_read_32 ((u_int32_t *) &comet->__res26); /* 0x98 */
break;
case 3:
data = pci_read_32 ((u_int32_t *) &comet->__res27); /* 0x9C */
break;
case 4:
data = pci_read_32 ((u_int32_t *) &comet->__res88); /* 0x220 */
break;
case 5:
data = pci_read_32 ((u_int32_t *) &comet->__res89); /* 0x224 */
break;
case 6:
data = pci_read_32 ((u_int32_t *) &comet->__res8A); /* 0x228 */
break;
case 7:
data = pci_read_32 ((u_int32_t *) &comet->__res8B); /* 0x22C */
break;
case 8:
data = pci_read_32 ((u_int32_t *) &comet->__resA0); /* 0x280 */
break;
case 9:
data = pci_read_32 ((u_int32_t *) &comet->__resA1); /* 0x284 */
break;
case 10:
data = pci_read_32 ((u_int32_t *) &comet->__resA2); /* 0x288 */
break;
case 11:
data = pci_read_32 ((u_int32_t *) &comet->__resA3); /* 0x28C */
break;
case 12:
data = pci_read_32 ((u_int32_t *) &comet->__resA4); /* 0x290 */
break;
case 13:
data = pci_read_32 ((u_int32_t *) &comet->__resA5); /* 0x294 */
break;
case 14:
data = pci_read_32 ((u_int32_t *) &comet->__resA6); /* 0x298 */
break;
case 15:
data = pci_read_32 ((u_int32_t *) &comet->__resA7); /* 0x29C */
break;
case 16:
data = pci_read_32 ((u_int32_t *) &comet->__res74); /* 0x1D0 */
break;
case 17:
data = pci_read_32 ((u_int32_t *) &comet->__res75); /* 0x1D4 */
break;
case 18:
data = pci_read_32 ((u_int32_t *) &comet->__res76); /* 0x1D8 */
break;
case 19:
data = pci_read_32 ((u_int32_t *) &comet->__res77); /* 0x1DC */
break;
}
}
