static void tnetw1130_init(pci_tnetw1130_t *d, NICInfo * nd)
{
tnetw1130_t *s = &d->tnetw1130;
/* TI TNETW1130 */
tnetw1130_pci_config(d->dev.config);
/* Handler for memory-mapped I/O */
s->io_memory[0] =
cpu_register_io_memory(0, tnetw1130_region0_read, tnetw1130_region0_write, d);
s->io_memory[1] =
cpu_register_io_memory(0, tnetw1130_region1_read, tnetw1130_region1_write, d);
TRACE(TNETW, logout("io_memory = 0x%08x, 0x%08x\n", s->io_memory[0], s->io_memory[1]));
pci_register_io_region(&d->dev, 0, TNETW1130_MEM0_SIZE,
PCI_ADDRESS_SPACE_MEM, tnetw1130_mem_map);
pci_register_io_region(&d->dev, 1, TNETW1130_MEM1_SIZE,
PCI_ADDRESS_SPACE_MEM, tnetw1130_mem_map);
static const char macaddr[6] = {
0x00, 0x60, 0x65, 0x02, 0x4a, 0x8e
};
memcpy(s->macaddr, macaddr, 6);
//~ memcpy(s->macaddr, nd->macaddr, 6);
tnetw1130_reset(s);
s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
tnetw1130_receive, tnetw1130_can_receive,
tnetw1130_cleanup, s);
qemu_format_nic_info_str(s->vc, s->macaddr);
qemu_register_reset(nic_reset, d);
register_savevm("tnetw1130", tnetw1130_instance, tnetw1130_version,
tnetw1130_save, tnetw1130_load, d);
}
/* EBUS (Eight bit bus) bridge */
static void
pci_ebus_init(PCIBus *bus, int devfn)
{
PCIDevice *s;
s = pci_register_device(bus, "EBUS", sizeof(*s), devfn, NULL, NULL);
pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
s->config[0x04] = 0x06; // command = bus master, pci mem
s->config[0x05] = 0x00;
s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
s->config[0x07] = 0x03; // status = medium devsel
s->config[0x08] = 0x01; // revision
s->config[0x09] = 0x00; // programming i/f
pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
s->config[0x0D] = 0x0a; // latency_timer
s->config[0x0E] = 0x00; // header_type
pci_register_io_region(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
ebus_mmio_mapfunc);
pci_register_io_region(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM,
ebus_mmio_mapfunc);
}
void vlynq_tnetw1130_init(void)
{
pci_tnetw1130_t *d = &vlynq;
uint8_t *pci_conf = d->dev.config;
tnetw1130_t *s = &d->tnetw1130;
#if defined(DEBUG_TNETW1130)
set_traceflags("DEBUG_AR7");
#endif
TRACE(TNETW, logout("\n"));
/* TI TNETW1130 */
tnetw1130_pci_config(pci_conf);
/* Handler for memory-mapped I/O */
s->io_memory[0] =
cpu_register_io_memory(0, tnetw1130_region0_read, tnetw1130_region0_write, d);
s->io_memory[1] =
cpu_register_io_memory(0, tnetw1130_region1_read, tnetw1130_region1_write, d);
TRACE(TNETW, logout("io_memory = 0x%08x, 0x%08x\n", s->io_memory[0], s->io_memory[1]));
pci_register_io_region(&d->dev, 0, TNETW1130_MEM0_SIZE,
PCI_ADDRESS_SPACE_MEM, tnetw1130_mem_map);
pci_register_io_region(&d->dev, 1, TNETW1130_MEM1_SIZE,
PCI_ADDRESS_SPACE_MEM, tnetw1130_mem_map);
memcpy(s->mem1 + 0x0001f000, pci_conf, 64);
/* eCPU is halted. */
reg_write16(s->mem0, TNETW1130_ECPU_CTRL, 1);
//~ tnetw1130_mem_map(&d->dev, 0, 0x04000000, 0x22000, 0); /* 0xf0000000 */
//~ tnetw1130_mem_map(&d->dev, 1, 0x04022000, 0x40000, 0); /* 0xc0000000 */
//~ tnetw1130_mem_map(&d->dev, 1, 0x04000000, 0x40000, 0);
//~ tnetw1130_mem_map(&d->dev, 0, 0x04040000, 0x22000, 0);
tnetw1130_mem_map(&d->dev, 0, 0x04000000, TNETW1130_MEM0_SIZE, 0);
tnetw1130_mem_map(&d->dev, 1, 0x04022000, TNETW1130_MEM1_SIZE, 0);
}
void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
int dbdma_mem_index, int cuda_mem_index, void *nvram,
int nb_ide, int *ide_mem_index, int escc_mem_index)
{
PCIDevice *d;
macio_state_t *macio_state;
int i;
d = pci_register_device(bus, "macio",
sizeof(PCIDevice) + sizeof(macio_state_t),
-1, NULL, NULL);
macio_state = (macio_state_t *)(d + 1);
macio_state->is_oldworld = is_oldworld;
macio_state->pic_mem_index = pic_mem_index;
macio_state->dbdma_mem_index = dbdma_mem_index;
macio_state->cuda_mem_index = cuda_mem_index;
macio_state->escc_mem_index = escc_mem_index;
macio_state->nvram = nvram;
if (nb_ide > 4)
nb_ide = 4;
macio_state->nb_ide = nb_ide;
for (i = 0; i < nb_ide; i++)
macio_state->ide_mem_index[i] = ide_mem_index[i];
for (; i < 4; i++)
macio_state->ide_mem_index[i] = -1;
/* Note: this code is strongly inspirated from the corresponding code
in PearPC */
d->config[0x00] = 0x6b; // vendor_id
d->config[0x01] = 0x10;
d->config[0x02] = device_id;
d->config[0x03] = device_id >> 8;
d->config[0x0a] = 0x00; // class_sub = pci2pci
d->config[0x0b] = 0xff; // class_base = bridge
d->config[0x0e] = 0x00; // header_type
d->config[0x3d] = 0x01; // interrupt on pin 1
pci_register_io_region(d, 0, 0x80000,
PCI_ADDRESS_SPACE_MEM, macio_map);
}