/* * Special API for POWER to configure the vectors through * a side channel. Should never be used by devices. */ void msix_set_message(PCIDevice *dev, int vector, struct MSIMessage msg) { uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE; pci_set_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR, msg.address); pci_set_long(table_entry + PCI_MSIX_ENTRY_DATA, msg.data); table_entry[PCI_MSIX_ENTRY_VECTOR_CTRL] &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; }
void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num) { static const int pci_dsn_ver = 1; static const int pci_dsn_cap = 4; pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset, PCI_EXT_CAP_DSN_SIZEOF); pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num); }
static void mch_reset(DeviceState *qdev) { PCIDevice *d = PCI_DEVICE(qdev); MCHPCIState *mch = MCH_PCI_DEVICE(d); pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; mch_update(mch); }