static void __init pirq_peer_trick(void) { struct irq_routing_table *rt = pirq_table; u8 busmap[256]; int i; struct irq_info *e; memset(busmap, 0, sizeof(busmap)); for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { e = &rt->slots[i]; #ifdef DEBUG { int j; DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); for (j = 0; j < 4; j++) DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); DBG("\n"); } #endif busmap[e->bus] = 1; } for (i = 1; i < 256; i++) { if (!busmap[i] || pci_find_bus(0, i)) continue; pcibios_scan_root(i); } pcibios_last_bus = -1; }
struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_device *device, int domain, int busnum) { if (domain != 0) { printk(KERN_WARNING "PCI: Multiple domains not supported\n"); return NULL; } return pcibios_scan_root(busnum); }
int __init pci_legacy_init(void) { if (!raw_pci_ops) { printk("PCI: System does not support PCI\n"); return 0; } printk("PCI: Probing PCI hardware\n"); pci_root_bus = pcibios_scan_root(0); return 0; }
static void pci_fixup_i450gx(struct pci_dev *d) { /* * i450GX and i450KX -- Find and scan all secondary buses. * (called separately for each PCI bridge found) */ u8 busno; pci_read_config_byte(d, 0x4a, &busno); dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno); pcibios_scan_root(busno); pcibios_last_bus = -1; }
int main(int argc, char** argv) { #ifdef CONFIG_NUMA nr_node_ids = rand() % (MAX_NUMNODES-1); #endif setup_node_to_cpumask_map(); #ifdef CONFIG_PCI int node = pcibios_scan_root(); dev_attr_show(node); #endif return 0; }
int __init pci_visws_init(void) { pcibios_enable_irq = &pci_visws_enable_irq; pcibios_disable_irq = &pci_visws_disable_irq; /* The VISWS supports configuration access type 1 only */ pci_probe = (pci_probe | PCI_PROBE_CONF1) & ~(PCI_PROBE_BIOS | PCI_PROBE_CONF2); pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff; pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff; printk(KERN_INFO "PCI: Lithium bridge A bus: %u, " "bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0); raw_pci_ops = &pci_direct_conf1; pcibios_scan_root(pci_bus0); pcibios_scan_root(pci_bus1); pci_fixup_irqs(pci_common_swizzle, visws_map_irq); pcibios_resource_survey(); /* Request bus scan */ return 1; }
static void pci_fixup_i450nx(struct pci_dev *d) { /* * i450NX -- Find and scan all secondary buses on all PXB's. */ int pxb, reg; u8 busno, suba, subb; dev_warn(&d->dev, "Searching for i450NX host bridges\n"); reg = 0xd0; for(pxb = 0; pxb < 2; pxb++) { pci_read_config_byte(d, reg++, &busno); pci_read_config_byte(d, reg++, &suba); pci_read_config_byte(d, reg++, &subb); dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb); if (busno) pcibios_scan_root(busno); /* Bus A */ if (suba < subb) pcibios_scan_root(suba+1); /* Bus B */ } pcibios_last_bus = -1; }
static int __init pci_legacy_init(void) { if (!raw_pci_ops) { printk("PCI: System does not support PCI\n"); return 0; } if (pcibios_scanned++) return 0; printk("PCI: Probing PCI hardware\n"); pci_root_bus = pcibios_scan_root(0); pcibios_fixup_peer_bridges(); return 0; }
void pcibios_scan_specific_bus(int busn) { int devfn; u32 l; if (pci_find_bus(0, busn)) return; for (devfn = 0; devfn < 256; devfn += 8) { if (!raw_pci_read(0, busn, devfn, PCI_VENDOR_ID, 2, &l) && l != 0x0000 && l != 0xffff) { DBG("Found device at %02x:%02x [%04x]\n", busn, devfn, l); printk(KERN_INFO "PCI: Discovered peer bus %02x\n", busn); pcibios_scan_root(busn); return; } } }