void __init ixdp2800_pci_preinit(void)
{
printk("ixdp2x00_pci_preinit called\n");
*IXP2000_PCI_ADDR_EXT = 0x0001e000;
if (!ixdp2x00_master_npu())
ixdp2800_slave_disable_pci_master();
*IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff;
*IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff;
ixp2000_pci_preinit();
if (ixdp2x00_master_npu()) {
/*
* Wait until the slave set its SRAM/SDRAM BAR sizes
* correctly before we proceed to scan and enumerate
* the bus.
*/
ixdp2800_master_wait_for_slave();
/*
* We configure the SDRAM BARs by hand because they
* are 1G and fall outside of the regular allocated
* PCI address space.
*/
*IXP2000_PCI_SDRAM_BAR = 0x00000008;
} else {
/*
* Wait for the master to complete scanning the bus
* and assigning resources before we proceed to scan
* the bus ourselves. Set pci=firmware to honor the
* master's resource assignment.
*/
ixdp2800_slave_wait_for_master_enable();
pcibios_setup("firmware");
}
}
static void __init enp2611_pci_preinit(void)
{
ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000);
ixp2000_pci_preinit();
pcibios_setup("firmware");
}
/*************************************************************************
* IXDP2x01 PCI
*************************************************************************/
void __init ixdp2x01_pci_preinit(void)
{
ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
ixp2000_pci_preinit();
pcibios_setup("firmware");
}
int __init l4vpci_setup(int nr, struct pci_sys_data *sys)
{
(void)sys;
pcibios_setup("firmware");
return nr == 0 ? 1 : 0;
}
