static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
{
if(pdev_is_sata(dev))
goto sata_skip;
printk(KERN_INFO "%s: BASE CLOCK ", name);
clocking &= 0x03;
switch(clocking) {
case 0x03: printk("DISABLED !\n"); break;
case 0x02: printk("== 2X PCI \n"); break;
case 0x01: printk("== 133 \n"); break;
case 0x00: printk("== 100 \n"); break;
}
sata_skip:
#if defined(DISPLAY_SIIMAGE_TIMINGS) && defined(CONFIG_PROC_FS)
siimage_devs[n_siimage_devs++] = dev;
if (!siimage_proc) {
siimage_proc = 1;
ide_pci_register_host_proc(&siimage_procs[0]);
}
#endif /* DISPLAY_SIIMAGE_TIMINGS && CONFIG_PROC_FS */
}
static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
{
struct pci_dev *dev = to_pci_dev(hwif->dev);
void *addr = pci_get_drvdata(dev);
u8 ch = hwif->channel;
struct ide_io_ports *io_ports = &hwif->io_ports;
unsigned long base;
/*
* Fill in the basic hwif bits
*/
hwif->host_flags |= IDE_HFLAG_MMIO;
default_hwif_mmiops(hwif);
hwif->hwif_data = addr;
/*
* Now set up the hw. We have to do this ourselves as the
* MMIO layout isn't the same as the standard port based I/O.
*/
memset(io_ports, 0, sizeof(*io_ports));
base = (unsigned long)addr;
if (ch)
base += 0xC0;
else
base += 0x80;
/*
* The buffered task file doesn't have status/control, so we
* can't currently use it sanely since we want to use LBA48 mode.
*/
io_ports->data_addr = base;
io_ports->error_addr = base + 1;
io_ports->nsect_addr = base + 2;
io_ports->lbal_addr = base + 3;
io_ports->lbam_addr = base + 4;
io_ports->lbah_addr = base + 5;
io_ports->device_addr = base + 6;
io_ports->status_addr = base + 7;
io_ports->ctl_addr = base + 10;
if (pdev_is_sata(dev)) {
base = (unsigned long)addr;
if (ch)
base += 0x80;
hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
}
hwif->irq = dev->irq;
hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
hwif->mmio = 1;
}
static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
{
if (!pdev_is_sata(dev)) {
printk(KERN_INFO "%s: BASE CLOCK ", name);
clocking &= 0x03;
switch (clocking) {
case 0x03: printk("DISABLED!\n"); break;
case 0x02: printk("== 2X PCI\n"); break;
case 0x01: printk("== 133\n"); break;
case 0x00: printk("== 100\n"); break;
}
}
}
static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
{
struct pci_dev *dev = to_pci_dev(hwif->dev);
struct ide_host *host = pci_get_drvdata(dev);
void *addr = host->host_priv;
u8 ch = hwif->channel;
struct ide_io_ports *io_ports = &hwif->io_ports;
unsigned long base;
hwif->host_flags |= IDE_HFLAG_MMIO;
hwif->hwif_data = addr;
memset(io_ports, 0, sizeof(*io_ports));
base = (unsigned long)addr;
if (ch)
base += 0xC0;
else
base += 0x80;
io_ports->data_addr = base;
io_ports->error_addr = base + 1;
io_ports->nsect_addr = base + 2;
io_ports->lbal_addr = base + 3;
io_ports->lbam_addr = base + 4;
io_ports->lbah_addr = base + 5;
io_ports->device_addr = base + 6;
io_ports->status_addr = base + 7;
io_ports->ctl_addr = base + 10;
if (pdev_is_sata(dev)) {
base = (unsigned long)addr;
if (ch)
base += 0x80;
hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
}
hwif->irq = dev->irq;
hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
}
static inline int is_sata(ide_hwif_t *hwif)
{
return pdev_is_sata(to_pci_dev(hwif->dev));
}
static int init_chipset_siimage(struct pci_dev *dev)
{
struct ide_host *host = pci_get_drvdata(dev);
void __iomem *ioaddr = host->host_priv;
unsigned long base, scsc_addr;
u8 rev = dev->revision, tmp;
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
if (ioaddr)
pci_set_master(dev);
base = (unsigned long)ioaddr;
if (ioaddr && pdev_is_sata(dev)) {
u32 tmp32, irq_mask;
irq_mask = (1 << 22) | (1 << 23);
tmp32 = readl(ioaddr + 0x48);
if (tmp32 & irq_mask) {
tmp32 &= ~irq_mask;
writel(tmp32, ioaddr + 0x48);
readl(ioaddr + 0x48);
}
writel(0, ioaddr + 0x148);
writel(0, ioaddr + 0x1C8);
}
sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
scsc_addr = base ? (base + 0x4A) : 0x8A;
tmp = sil_ioread8(dev, scsc_addr);
switch (tmp & 0x30) {
case 0x00:
sil_iowrite8(dev, tmp | 0x10, scsc_addr);
break;
case 0x30:
sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
case 0x10:
break;
case 0x20:
break;
}
tmp = sil_ioread8(dev, scsc_addr);
sil_iowrite8 (dev, 0x72, base + 0xA1);
sil_iowrite16(dev, 0x328A, base + 0xA2);
sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
sil_iowrite32(dev, 0x43924392, base + 0xA8);
sil_iowrite32(dev, 0x40094009, base + 0xAC);
sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
if (base && pdev_is_sata(dev)) {
writel(0xFFFF0000, ioaddr + 0x108);
writel(0xFFFF0000, ioaddr + 0x188);
writel(0x00680000, ioaddr + 0x148);
writel(0x00680000, ioaddr + 0x1C8);
}
if (!pdev_is_sata(dev)) {
static const char *clk_str[] =
{ "== 100", "== 133", "== 2X PCI", "DISABLED!" };
tmp >>= 4;
printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n",
pci_name(dev), clk_str[tmp & 3]);
}
return 0;
}
static int init_chipset_siimage(struct pci_dev *dev)
{
struct ide_host *host = pci_get_drvdata(dev);
void __iomem *ioaddr = host->host_priv;
unsigned long base, scsc_addr;
u8 rev = dev->revision, tmp;
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
if (ioaddr)
pci_set_master(dev);
base = (unsigned long)ioaddr;
if (ioaddr && pdev_is_sata(dev)) {
u32 tmp32, irq_mask;
/* make sure IDE0/1 interrupts are not masked */
irq_mask = (1 << 22) | (1 << 23);
tmp32 = readl(ioaddr + 0x48);
if (tmp32 & irq_mask) {
tmp32 &= ~irq_mask;
writel(tmp32, ioaddr + 0x48);
readl(ioaddr + 0x48); /* flush */
}
writel(0, ioaddr + 0x148);
writel(0, ioaddr + 0x1C8);
}
sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
scsc_addr = base ? (base + 0x4A) : 0x8A;
tmp = sil_ioread8(dev, scsc_addr);
switch (tmp & 0x30) {
case 0x00:
/* On 100 MHz clocking, try and switch to 133 MHz */
sil_iowrite8(dev, tmp | 0x10, scsc_addr);
break;
case 0x30:
/* Clocking is disabled, attempt to force 133MHz clocking. */
sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
case 0x10:
/* On 133Mhz clocking. */
break;
case 0x20:
/* On PCIx2 clocking. */
break;
}
tmp = sil_ioread8(dev, scsc_addr);
sil_iowrite8 (dev, 0x72, base + 0xA1);
sil_iowrite16(dev, 0x328A, base + 0xA2);
sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
sil_iowrite32(dev, 0x43924392, base + 0xA8);
sil_iowrite32(dev, 0x40094009, base + 0xAC);
sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
if (base && pdev_is_sata(dev)) {
writel(0xFFFF0000, ioaddr + 0x108);
writel(0xFFFF0000, ioaddr + 0x188);
writel(0x00680000, ioaddr + 0x148);
writel(0x00680000, ioaddr + 0x1C8);
}
/* report the clocking mode of the controller */
if (!pdev_is_sata(dev)) {
static const char *clk_str[] =
{ "== 100", "== 133", "== 2X PCI", "DISABLED!" };
tmp >>= 4;
printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n",
pci_name(dev), clk_str[tmp & 3]);
}
return 0;
}
static void __init init_mmio_iops_siimage (ide_hwif_t *hwif)
{
struct pci_dev *dev = hwif->pci_dev;
void *addr = pci_get_drvdata(dev);
u8 ch = hwif->channel;
hw_regs_t hw;
unsigned long base;
/*
* Fill in the basic HWIF bits
*/
default_hwif_mmiops(hwif);
hwif->hwif_data = addr;
/*
* Now set up the hw. We have to do this ourselves as
* the MMIO layout isnt the same as the the standard port
* based I/O
*/
memset(&hw, 0, sizeof(hw_regs_t));
hw.priv = addr;
base = (unsigned long)addr;
if(ch)
base += 0xC0;
else
base += 0x80;
/*
* The buffered task file doesn't have status/control
* so we can't currently use it sanely since we want to
* use LBA48 mode.
*/
// base += 0x10;
// hwif->addressing = 1;
hw.io_ports[IDE_DATA_OFFSET] = base;
hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
hw.io_ports[IDE_IRQ_OFFSET] = 0;
if (pdev_is_sata(dev)) {
base = (unsigned long) addr;
if(ch)
base += 0x80;
hw.sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
hw.sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
hw.sata_scr[SATA_CONTROL_OFFSET]= base + 0x100;
hw.sata_misc[SATA_MISC_OFFSET] = base + 0x140;
hw.sata_misc[SATA_PHY_OFFSET] = base + 0x144;
hw.sata_misc[SATA_IEN_OFFSET] = base + 0x148;
}
hw.irq = hwif->pci_dev->irq;
memcpy(&hwif->hw, &hw, sizeof(hw));
memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
if (is_sata(hwif)) {
memcpy(hwif->sata_scr, hwif->hw.sata_scr, sizeof(hwif->hw.sata_scr));
memcpy(hwif->sata_misc, hwif->hw.sata_misc, sizeof(hwif->hw.sata_misc));
}
hwif->irq = hw.irq;
base = (unsigned long) addr;
#ifdef SIIMAGE_LARGE_DMA
/* Watch the brackets - even Ken and Dennis get some language design wrong */
hwif->dma_base = base + (ch ? 0x18 : 0x10);
hwif->dma_base2 = base + (ch ? 0x08 : 0x00);
hwif->dma_prdtable = hwif->dma_base2 + 4;
#else /* ! SIIMAGE_LARGE_DMA */
hwif->dma_base = base + (ch ? 0x08 : 0x00);
hwif->dma_base2 = base + (ch ? 0x18 : 0x10);
#endif /* SIIMAGE_LARGE_DMA */
hwif->mmio = 2;
}
static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
{
unsigned long bar5 = pci_resource_start(dev, 5);
unsigned long barsize = pci_resource_len(dev, 5);
u8 tmpbyte = 0;
unsigned long addr;
void *ioaddr;
/*
* Drop back to PIO if we can't map the mmio. Some
* systems seem to get terminally confused in the PCI
* spaces.
*/
if(!request_mem_region(bar5, barsize, name))
{
printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
return 0;
}
ioaddr = ioremap(bar5, barsize);
if (ioaddr == NULL)
{
release_mem_region(bar5, barsize);
return 0;
}
pci_set_master(dev);
pci_set_drvdata(dev, ioaddr);
addr = (unsigned long) ioaddr;
if (pdev_is_sata(dev)) {
writel(0, addr + 0x148);
writel(0, addr + 0x1C8);
}
writeb(0, addr + 0xB4);
writeb(0, addr + 0xF4);
tmpbyte = readb(addr + 0x4A);
switch(tmpbyte & 0x30) {
case 0x00:
/* In 100 MHz clocking, try and switch to 133 */
writeb(tmpbyte|0x10, addr + 0x4A);
break;
case 0x10:
/* On 133Mhz clocking */
break;
case 0x20:
/* On PCIx2 clocking */
break;
case 0x30:
/* Clocking is disabled */
/* 133 clock attempt to force it on */
writeb(tmpbyte & ~0x20, addr + 0x4A);
break;
}
writeb( 0x72, addr + 0xA1);
writew( 0x328A, addr + 0xA2);
writel(0x62DD62DD, addr + 0xA4);
writel(0x43924392, addr + 0xA8);
writel(0x40094009, addr + 0xAC);
writeb( 0x72, addr + 0xE1);
writew( 0x328A, addr + 0xE2);
writel(0x62DD62DD, addr + 0xE4);
writel(0x43924392, addr + 0xE8);
writel(0x40094009, addr + 0xEC);
if (pdev_is_sata(dev)) {
writel(0xFFFF0000, addr + 0x108);
writel(0xFFFF0000, addr + 0x188);
writel(0x00680000, addr + 0x148);
writel(0x00680000, addr + 0x1C8);
}
tmpbyte = readb(addr + 0x4A);
proc_reports_siimage(dev, (tmpbyte>>4), name);
return 1;
}
static inline int is_sata(ide_hwif_t *hwif)
{
return pdev_is_sata(hwif->pci_dev);
}
static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
{
struct pci_dev *dev = hwif->pci_dev;
void *addr = pci_get_drvdata(dev);
u8 ch = hwif->channel;
hw_regs_t hw;
unsigned long base;
/*
* Fill in the basic HWIF bits
*/
default_hwif_mmiops(hwif);
hwif->hwif_data = addr;
/*
* Now set up the hw. We have to do this ourselves as
* the MMIO layout isnt the same as the the standard port
* based I/O
*/
memset(&hw, 0, sizeof(hw_regs_t));
base = (unsigned long)addr;
if (ch)
base += 0xC0;
else
base += 0x80;
/*
* The buffered task file doesn't have status/control
* so we can't currently use it sanely since we want to
* use LBA48 mode.
*/
hw.io_ports[IDE_DATA_OFFSET] = base;
hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
hw.io_ports[IDE_IRQ_OFFSET] = 0;
if (pdev_is_sata(dev)) {
base = (unsigned long)addr;
if (ch)
base += 0x80;
hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140;
hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144;
hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148;
}
memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports));
hwif->irq = dev->irq;
hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
hwif->mmio = 2;
}