struct pipe_resource *si_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
struct radeon_surface surface;
unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
int r;
#if 0
if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
!(templ->bind & PIPE_BIND_SCANOUT)) {
if (permit_hardware_blit(screen, templ)) {
array_mode = V_009910_ARRAY_2D_TILED_THIN1;
}
}
#endif
r = r600_init_surface(&surface, templ, array_mode);
if (r) {
return NULL;
}
r = rscreen->ws->surface_best(rscreen->ws, &surface);
if (r) {
return NULL;
}
return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
0, 0, NULL, TRUE, &surface);
}
static struct r600_resource_texture *
r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
unsigned array_mode,
unsigned pitch_in_bytes_override,
unsigned max_buffer_size,
struct pb_buffer *buf,
boolean alloc_bo,
struct radeon_surface *surface)
{
struct r600_resource_texture *rtex;
struct si_resource *resource;
struct r600_screen *rscreen = (struct r600_screen*)screen;
int r;
rtex = CALLOC_STRUCT(r600_resource_texture);
if (rtex == NULL)
return NULL;
resource = &rtex->resource;
resource->b.b = *base;
resource->b.vtbl = &r600_texture_vtbl;
pipe_reference_init(&resource->b.b.reference, 1);
resource->b.b.screen = screen;
rtex->pitch_override = pitch_in_bytes_override;
rtex->real_format = base->format;
/* only mark depth textures the HW can hit as depth textures */
if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
rtex->depth = 1;
r600_setup_miptree(screen, rtex, array_mode);
rtex->surface = *surface;
r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
if (r) {
FREE(rtex);
return NULL;
}
/* Now create the backing buffer. */
if (!buf && alloc_bo) {
struct pipe_resource *ptex = &rtex->resource.b.b;
unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
base_align = rtex->surface.bo_alignment;
if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
FREE(rtex);
return NULL;
}
} else if (buf) {
resource->buf = buf;
resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
}
return rtex;
}
static struct pipe_transfer* si_texture_get_transfer(struct pipe_context *ctx,
struct pipe_resource *texture,
unsigned level,
unsigned usage,
const struct pipe_box *box)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
struct pipe_resource resource;
struct r600_transfer *trans;
int r;
boolean use_staging_texture = FALSE;
/* We cannot map a tiled texture directly because the data is
* in a different order, therefore we do detiling using a blit.
*
* Also, use a temporary in GTT memory for read transfers, as
* the CPU is much happier reading out of cached system memory
* than uncached VRAM.
*/
if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED &&
rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR)
use_staging_texture = TRUE;
if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
use_staging_texture = TRUE;
/* XXX: Use a staging texture for uploads if the underlying BO
* is busy. No interface for checking that currently? so do
* it eagerly whenever the transfer doesn't require a readback
* and might block.
*/
if ((usage & PIPE_TRANSFER_WRITE) &&
!(usage & (PIPE_TRANSFER_READ |
PIPE_TRANSFER_DONTBLOCK |
PIPE_TRANSFER_UNSYNCHRONIZED)))
use_staging_texture = TRUE;
if (!permit_hardware_blit(ctx->screen, texture) ||
(texture->flags & R600_RESOURCE_FLAG_TRANSFER))
use_staging_texture = FALSE;
if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
return NULL;
trans = CALLOC_STRUCT(r600_transfer);
if (trans == NULL)
return NULL;
pipe_resource_reference(&trans->transfer.resource, texture);
trans->transfer.level = level;
trans->transfer.usage = usage;
trans->transfer.box = *box;
if (rtex->depth) {
/* XXX: only readback the rectangle which is being mapped?
*/
/* XXX: when discard is true, no need to read back from depth texture
*/
r = r600_texture_depth_flush(ctx, texture, FALSE);
if (r < 0) {
R600_ERR("failed to create temporary texture to hold untiled copy\n");
pipe_resource_reference(&trans->transfer.resource, NULL);
FREE(trans);
return NULL;
}
trans->transfer.stride = rtex->flushed_depth_texture->surface.level[level].pitch_bytes;
trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
return &trans->transfer;
} else if (use_staging_texture) {
resource.target = PIPE_TEXTURE_2D;
resource.format = texture->format;
resource.width0 = box->width;
resource.height0 = box->height;
resource.depth0 = 1;
resource.array_size = 1;
resource.last_level = 0;
resource.nr_samples = 0;
resource.usage = PIPE_USAGE_STAGING;
resource.bind = 0;
resource.flags = R600_RESOURCE_FLAG_TRANSFER;
/* For texture reading, the temporary (detiled) texture is used as
* a render target when blitting from a tiled texture. */
if (usage & PIPE_TRANSFER_READ) {
resource.bind |= PIPE_BIND_RENDER_TARGET;
}
/* For texture writing, the temporary texture is used as a sampler
* when blitting into a tiled texture. */
if (usage & PIPE_TRANSFER_WRITE) {
resource.bind |= PIPE_BIND_SAMPLER_VIEW;
}
/* Create the temporary texture. */
trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
if (trans->staging_texture == NULL) {
R600_ERR("failed to create temporary texture to hold untiled copy\n");
pipe_resource_reference(&trans->transfer.resource, NULL);
FREE(trans);
return NULL;
}
trans->transfer.stride = ((struct r600_resource_texture *)trans->staging_texture)
->surface.level[0].pitch_bytes;
if (usage & PIPE_TRANSFER_READ) {
r600_copy_to_staging_texture(ctx, trans);
/* Always referenced in the blit. */
radeonsi_flush(ctx, NULL, 0);
}
return &trans->transfer;
}
trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
trans->offset = r600_texture_get_offset(rtex, level, box->z);
return &trans->transfer;
}
